HK103688A

HK103688A - System for the transmission of digital information signals

Info

Publication number: HK103688A
Application number: HK1036/88A
Authority: HK
Inventors: Herman Wilhelm Werner Dipl.-Ing. Korte; Dieter Dipl.-Ing. Stark
Original assignee: Telefunken Fernseh Und Rundfunk Gmbh
Priority date: 1981-09-03
Filing date: 1988-12-22
Publication date: 1988-12-30
Also published as: DE3268027D1; JPS5851642A; EP0073979B1; SG64888G; EP0073979A1; DE3134831A1; JPH0365698B2; ATE17068T1

Abstract

1. System for the transmission of digital information signals, especially for digital sound transmission by satellites, having an encoder at the sending side and a decoder at the receiving side, in which the information signals to be transmitted are combined with a generator polynomial at the sending side in such a way that check places are associated with the information signals to be transmitted which are established from an arithmetical combination of the information signal with the generator polynomial, characterized in that a primitive BCH - code is used having the block length of 63 bits an 18 check places, of which the generator polynomial x**18 + x**17 + x**16 + x**15 + x**9 + x**7 + x**6 + x**3 + x**2 + x**1 + 1 is multiplicatively combined with the further generator polynomial x + 1, so that a generator polynomial for the encoder x**19 + x**15 + x**10 + x**9 + x**8 + x**6 + x**4 + 1 arises having a block length of 63 bits and 19 check places, so that at the receiving side as a result of the use of different decoding strategies there is carried out the correction of three errors and the recognition of four errors or the correction of two errors and the recognition of five errors or the correction of one error and the recognition of six errors or the recognition of seven errors, whereby the error recognition is used for the initiation of an error concealment measure.

Description

The invention relates to a transmission system and a circuit assembly for the encoding and decoding of digital information signals, particularly for digital audio transmission via satellites.

It is known that cyclic codes are used in the transmission of digital data signals to correct statistically distributed errors. The advantages of these codes are the linear systematic block construction with not too large redundancy and the easy implementation by means of back-coupled slider registers.

In digital information transmission, e.g. via satellites, only statistically distributed single-bit errors (Gaussian noise) occur, as described in British Telecommunications: OTS and Digital Television Transmittion Investigation of Error Statistics relevant to the design of Error Correctors for Television (20.11.80) .

DE-A1- 26 57 826 describes a device for detecting and correcting two-bit errors and a triple error detection.

A valid BCH code generator polynomial is generated with enhanced error detection and correction, and a parity bit is added to the BCH code to detect a third error that, when it occurs, will cause the decoder to shut down and not interpolate.

The purpose of the invention is to find a system which, under specified quality criteria, allows an improved error correction system for digital information transmission and is characterised by low circuitry effort of the coder and decoder.

This problem is solved by the invention mentioned in claim 1.

Beneficial continuing education of the invention is given in the subclaims.

The system of the present invention is characterized by the fact that by arithmetically linking the BCH code fully described by its generator polynomial with another generator polynomial, the minimum Hamming distance is extended and thus an increased error detection than with the original BCH code. The quality criteria required, for example, in the digital transmission of information via satellites are met and partially exceeded.

For g < i, two cases are distinguished: If more than g-bit errors occur in a block, the decoded information signal is distorted by a generally minor in-polation error.

The following quality criteria are postulated: the time average should be no more than one interpolation error per second and the average transmission time without crack interference should be one hour.

An example of how the system is implemented will be used to explain it in more detail.

It shows: Figure 1 shows a decoder circuit and Figure 2 shows a table.

In the case of digital information transmission via satellites, for example, 16 PCM stereo channels are transmitted simultaneously.

The information signals may be a sequence of data words from a bundle of stereo signals to be transmitted, two stereo channels or four monosignals, each summarising four data words of the information signals.

A known BCH code 63/45 is capable of encoding 45 bits of information. The generator polynomial of the known BCH code 63/45 is multiplied by the generator polynomial x + 1 according to the invention, thus increasing the minimum Hamming distance to dmin = 8. This results in the modified BCH code 63/44 according to the invention.

The information bits of the selected BCH code 63/44 result in the 14 bits of a PCM scan being split into 11 higher-value bits transmitted protected and three lower-value bits transmitted unprotected.

The choice of the BCH code 63/44 of the invention results in a system reserve characterised by the increased minimum Hamming distance dm;n = 8, which gives an additional degree of freedom in the choice of the decoding algorithm.

By dividing the 1. detectable and correctable and 2. only detectable bit errors, the following variants of the decoding of the BCH code 63/44 according to the invention are given in Figure 2.A: Three errors per block are correctable and a total of four errors per block are detectable.B: Two errors per block are correctable and a total of five errors per block are detectable.C: One error per block is correctable and a total of six errors per block are detectable.D: A total of seven errors per block are detectable.

For decoding variants A and B, the quality criteria of residual error probabilities for a channel error probability of 10-3 are met.

The average transmission time without any interference is 0.03 s. This results in an interpolation rate of 33/s. Based on a bit error probability of 10-3 of the transmission channel, an average transmission time without any interference of more than 5 days is achieved. The average transmission time without any interference is about 1 second, i.e. the interpolation rate is 1 /s.

The BCH code 63/44 has a block length of 63 bits. The information to be transmitted is encoded with k = 44 bits. The remaining 19 bits are test points. The Commission has not yet published a complete description of the measures taken.

The two-stage design of the decoder, which decodes the incoming information signals according to the above-mentioned variant B, is explained in more detail below using the figure.

Figure 1 shows a decoder circuit. The incoming information signals are fed through an input clamp 1 to an input 2 of an AND gate 3. Another input 4 of the AND gate 3 is connected to both an input clamp 5 and an inverting input 6 of an AND gate 9. The output 7 of the AND gate 3 is connected to an input 8 of a memory 17 and to an input 13 of an OR gate 14. The output 11 of the AND gate 9 is connected to both an additional input 12 of the OR gate 14 and an input 22 of an EXOR gate 20. The output 18 of the EXOR gate 17 is connected to an input 19 of the OR gate 20.The output 15 of OR gate 14 leads to input 16 of a back-coupled memory 23. The outputs 24 corresponding to the degree of the back-coupled memory 23 lead to both corresponding inputs 28 of a fixed value memory 29 and to inputs 25 of an OR gate 26. The output 27 of OR gate 26 leads to an input 33 of an OR gate 38. The output 30 of the fixed value memory 29 leads to another input 10 of the AND gate 9. The output 21 of EXOR gate 20 is connected to an output 37 and to the input 31 of another back-coupled memory 32. The output 32 corresponding to the degree of the back-coupled memory 32 is connected to a number of 34 inputs connected to 39 inputs of the 38-speed.The OR gate 38 exit 35 is connected to an exit 36 through which an interpolation call can be made.

The decoder checks the 63-bit codeword to be decoded for divisibility by the generator polynomial using the back-coupled memory 23 and 32. The first stage, in which an error can be detected and corrected, consists of AND gates 3 and 9, OR gates 14 and 26, EXOR gate 20, memory 17, back-coupled memory 23 and fixed-value memory 29.

Simultaneously with the input to memory 17, the incoming data is read from OR gate 14 into the back-coupled memory 23 and the 63-bit codeword is checked for divisible by the partial polynomial E in the back-coupled memory 23.

After the input phase, which is 63 beats long, a logical 0 is created at input 5. The AN D-gate 3 is thus blocked for further incoming data at input 1. Now the correcting and selection phase begins. The syndrome detected in the back-coupled memory 23 indicates existing errors. The syndromes reversibly unambiguously assigned to the correcting error patterns in the correcting position are predicted and marked as fixed value memory 29 addresses. The outputs 24 of the back-coupled memory 23 are connected to the addresses 28 of fixed value memory 29, so that whenever a display pattern in synchrony is reached by the fixed value memory 29 cortex, a logical error or error correction may appear at the fixed value memory 291 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Since the information bits are read out from the 63-bit memory 17 in a tactile manner during the correction and read-out phase, the detected faulty bit is located at the input 19 of EXOR gate 20 when a correction signal is present at the output 30 of fixed-value memory 29. The faulty bit is then corrected by the EXOR gate 20 via the AND gate 9. At the same time, the corresponding OR syndrome in the back-coupled memory 23 is corrected via the gate 14. After correction of the faulty bit and the syndrome, further identified syndromes are examined.

If more than two errors are detected, the correction capability of the first stage is exhausted. At the outputs 24 of the back-coupled memory 23 there is an error pattern indicating another error. After the correction and selection phase is completed, an interpolation call is made via OR gate 26 and OR gate 38.

The second stage, the error detection stage, consists of the back-coupled memory 32, the OR gate 38 and the output 36. The data read from memory 17 are simultaneously read into the back-coupled memory 32. There they are checked for divisibility by the partial polynomial F. If the test result indicates a syndrome not equal to zero, an interpolation call is made at the end of the selection phase via the output 36 so that the faulty sampling value can be corrected in a subsequent switched interpolation stage in such a way that the faulty value is replaced by the mean of the previous and subsequent sampling values: In the second stage, it is possible to detect three more errors and to interpolate after the selection phase has expired.

After all 63 bits from memory 17 have been read, in case of non-zero syndrome, a further interpolation call is made in the first stage via OR gates 26 and 38. This case occurs in some cases with more than five errors, if the faulty code word cannot be assigned to a correction range. In this case, an interpolation call is also made, so that the average transmission time increases without crack interference.

The partial polynomial E multiplied by the partial polynomial F gives the generator polynomial of the BCH code 63/44 for the encoder.

The back-coupled memory 23 in Fig. 1 requires 12 flip-flops, while the fixed-value memory 29 has 212 storage locations. When using the generator polynomial for decoder variant A, the number of flip-flops increases to 18.

Since the error correction for decoder variant B can only produce 63 characteristic syndromes, there is a big difference in the number of memory slots available in the fixed value memory 29. To minimize the hardware effort for the syndrome detection, the fixed value memory 29 can be replaced by a multi-stage switch network in gate-array technology.

The system of the present invention is not only suitable for satellite transmission but is also applicable to all other information channels in which statistically distributed single-bit errors (Gaussian noise) occur.

Claims

1. System for the transmission of digital information signals, especially for digital sound transmission by satellites, having an encoder at the sending side and a decoder at the receiving side, in which the information signals to be transmitted are combined with a generator polynomial at the sending side in such a way that check places are associated with the information signals to be transmitted which are established from an arithmetical combination of the information signal with the generator polynomial, characterized in that a primitive BCH - code is used having the block length of 63 bits an 18 check places, of which the generator polynomial is multiplicatively combined with the further generator polynomial x + 1, so that a generator polynomial for the encoder arises having a block length of 63 bits and 19 check places, so that at the receiving side as a result of the use of different decoding strategies there is carried out the correction of three errors and the recognition of four errors or the correction of two errors and the recognition of five errors or the correction of one error and the recognition of six errors or the recognition of seven errors, whereby the error recognition is used for the initiation of an error concealment measure.

2. System according to Claim 1, characterized in that the information signals exhibit a sequence of data words from a bundle of stereo signals to be transmitted on two stereo channels or of four mono signals, whereby four data words of the information signals are collected together.

3. System according to Claim 2, characterized in that each data word of a single channel, which comprises 14 bits, is separated into eleven higher value bits and three lower value bits and only the four eleven high value bits which are arranged against one another in a row are combined with the cyclic code.

4. Circuit arrangement for the realisation of the system according to Claim 1, characterized in that the incoming information signals are applied to a first stage of the decoder, in which a part of the errors occurring in the incoming information signals is recognised and corrected, and directly thereupon are applied to a second stage, in which a further part of the errors are recognised.

5. Circuit according to Claim 4, characterized in that there is connected to the second stage an interpolation stage in which a data word of the incoming information signal, recognised as being incorrect but no longer capable of correction, is interpolated linearly or to a higher order by utilising codewords adjacent in time.

6. Circuit according to Claim 4, characterized in that the first stage of the decoder comprises a first store (17) and a second, back coupled store (23) in which the incoming information signals are written simultaneously.

7. Circuit according to Claim 4, characterized in that the information signals on being written in the second, back coupled store (23) are combined arithmetically with a first part polynomial (E).

8. Circuit according to Claim 7, characterized in that the first part-polynomial (E) is a polynomial

9. Circuit according to Claim 7, characterized in that after writing the information signals in the first store (17) and in the second, back coupled store (23) the information signals are tested as regards the syndrome equal to zero in a fixed value store (29) coupled to the outputs (24) of the second, back coupled store (23).

10. Circuit according to Claim 9, characterized in that upon the occurrence of a transmission error associated with a bit error, an address of the fixed value store (29) is called upon which sets up at the output (30) of the fixed value store (29) a correction signal and that with the aid of the correction signal a bit error and the syndrome associated with the error pattern are corrected.

11. Circuit according to Claim 10, characterized in that on the occurrence of the derived correction signal at the output (30) of the fixed value store (29), the incorrect bit of the information signal at the output (18) of the first store (17) is corrected by way of the gate (20).

12. Circuit according to Claim 4, characterized in that the information signals read from the first store (17) can be extracted at an output (37) and are written simultaneously in a third, back coupled store (32) of the second stage.

13. Circuit according to Claim 12, characterized in that the information signals, upon being written in the third, back coupled store, are combined arithmetically with a second part-polynomial (F).

14. Circuit according to Claim 13, charaterized in that the second part-polynomial is a polynomial

15. Circuit according to Claim 11, characterized in that upon the occurrence of a syndrome not equal to zero at the outputs (34) of the third, back coupled store (32) a signal for an initiation of interpolation is established by way of a gate (38).

16. Circuit according to Claim 10, characterized in that upon the overstepping of the capacity of the first stage for correction and after the expiry of the correction and reading phase, an interpolation initiation is put in hand by way of a gate (26) and a gate (38).

17. Circuit according to Claim 17, characterized in that a coder for the encoding of the digital information signals is employed at the sending side.

18. Circuit according to Claim 17, characterized in that a code is used having a generator polynomial of the following form