HK1036712A1 - Phase difference magnifier - Google Patents

Phase difference magnifier Download PDF

Info

Publication number
HK1036712A1
HK1036712A1 HK01107536A HK01107536A HK1036712A1 HK 1036712 A1 HK1036712 A1 HK 1036712A1 HK 01107536 A HK01107536 A HK 01107536A HK 01107536 A HK01107536 A HK 01107536A HK 1036712 A1 HK1036712 A1 HK 1036712A1
Authority
HK
Hong Kong
Prior art keywords
signal
predetermined time
delayed
input
output
Prior art date
Application number
HK01107536A
Other languages
German (de)
English (en)
French (fr)
Chinese (zh)
Other versions
HK1036712B (en
Inventor
Andrew M. Volk
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of HK1036712A1 publication Critical patent/HK1036712A1/en
Publication of HK1036712B publication Critical patent/HK1036712B/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
HK01107536.5A 1998-10-27 1999-10-06 Phase difference magnifier HK1036712B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US181034 1998-10-27
US09/181,034 US6128359A (en) 1998-10-27 1998-10-27 Phase difference magnifier
PCT/US1999/023344 WO2000025472A1 (en) 1998-10-27 1999-10-06 Phase difference magnifier

Publications (2)

Publication Number Publication Date
HK1036712A1 true HK1036712A1 (en) 2002-01-11
HK1036712B HK1036712B (en) 2006-12-08

Family

ID=

Also Published As

Publication number Publication date
TW444427B (en) 2001-07-01
KR20010080912A (ko) 2001-08-25
EP1125391A4 (en) 2003-01-29
DE69931512T2 (de) 2006-10-05
AU6510199A (en) 2000-05-15
DE69931512D1 (de) 2006-06-29
KR100419795B1 (ko) 2004-02-21
CN1166109C (zh) 2004-09-08
EP1125391A1 (en) 2001-08-22
CN1324534A (zh) 2001-11-28
WO2000025472A1 (en) 2000-05-04
US6128359A (en) 2000-10-03
EP1125391B1 (en) 2006-05-24

Similar Documents

Publication Publication Date Title
US7123051B1 (en) Soft core control of dedicated memory interface hardware in a programmable logic device
US7590008B1 (en) PVT compensated auto-calibration scheme for DDR3
US5834956A (en) Core clock correction in a 2/N mode clocking scheme
US6294937B1 (en) Method and apparatus for self correcting parallel I/O circuitry
US8661285B2 (en) Dynamically calibrated DDR memory controller
KR101144519B1 (ko) 앞선 위상 등화를 이용한 dll 위상 검출
US9041446B2 (en) Power savings mode for memory systems
KR20030033070A (ko) 버퍼가 장착된 메모리 시스템에서 신뢰성있는 전송을제공하기 위한 시스템 및 방법
US6114887A (en) Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US7292500B2 (en) Reducing read data strobe latency in a memory system
US6640310B2 (en) Clock system for multiple component system
US12230362B2 (en) Memory component with programmable data-to-clock ratio
EP1125391B1 (en) Phase difference magnifier
CN116049061B (zh) 一种跨时钟域的数据传输方法、系统、芯片及电子设备
US6954870B2 (en) Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface
US6877103B2 (en) Bus interface timing adjustment device, method and application chip
HK1036712B (en) Phase difference magnifier
US5826067A (en) Method and apparatus for preventing logic glitches in a 2/n clocking scheme
US5821784A (en) Method and apparatus for generating 2/N mode bus clock signals
US7376855B1 (en) Fully stable clock domain synchronization technique for input/output data transmission
US20030133528A1 (en) Aligned clock forwarding scheme
HK1063230B (en) Memory system, buffering device and method operating a memory system

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20101006