HK1024067A1 - Data processing system. - Google Patents

Data processing system.

Info

Publication number
HK1024067A1
HK1024067A1 HK00103021A HK00103021A HK1024067A1 HK 1024067 A1 HK1024067 A1 HK 1024067A1 HK 00103021 A HK00103021 A HK 00103021A HK 00103021 A HK00103021 A HK 00103021A HK 1024067 A1 HK1024067 A1 HK 1024067A1
Authority
HK
Hong Kong
Prior art keywords
data processing
processing system
data
processing
Prior art date
Application number
HK00103021A
Other languages
English (en)
Inventor
Robert George Stranger
Jonathan Mark Saunders
Parminder Singh Guraya
Original Assignee
Marconi Uk Intellectual Prop
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Uk Intellectual Prop filed Critical Marconi Uk Intellectual Prop
Publication of HK1024067A1 publication Critical patent/HK1024067A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
HK00103021A 1998-08-13 2000-05-22 Data processing system. HK1024067A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9817598A GB2340627B (en) 1998-08-13 1998-08-13 Data processing system

Publications (1)

Publication Number Publication Date
HK1024067A1 true HK1024067A1 (en) 2000-09-29

Family

ID=10837155

Family Applications (1)

Application Number Title Priority Date Filing Date
HK00103021A HK1024067A1 (en) 1998-08-13 2000-05-22 Data processing system.

Country Status (8)

Country Link
US (1) US6519710B1 (ru)
EP (1) EP0980040B1 (ru)
CN (1) CN1154944C (ru)
DE (1) DE69908717T2 (ru)
ES (1) ES2199527T3 (ru)
GB (1) GB2340627B (ru)
HK (1) HK1024067A1 (ru)
RU (1) RU99118019A (ru)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3982353B2 (ja) * 2002-07-12 2007-09-26 日本電気株式会社 フォルトトレラントコンピュータ装置、その再同期化方法及び再同期化プログラム
EP1570599B1 (en) * 2002-11-27 2010-11-03 The Board of Governors for Higher Education State of Rhode Island and Providence Plantations System and method of digital system performance enhancement
US7287184B2 (en) * 2003-09-16 2007-10-23 Rockwell Automation Technologies, Inc. High speed synchronization in dual-processor safety controller
US7346759B1 (en) 2004-08-06 2008-03-18 Xilinx, Inc. Decoder interface
US7590822B1 (en) 2004-08-06 2009-09-15 Xilinx, Inc. Tracking an instruction through a processor pipeline
US7243212B1 (en) * 2004-08-06 2007-07-10 Xilinx, Inc. Processor-controller interface for non-lock step operation
US7590823B1 (en) 2004-08-06 2009-09-15 Xilinx, Inc. Method and system for handling an instruction not supported in a coprocessor formed using configurable logic
US7546441B1 (en) 2004-08-06 2009-06-09 Xilinx, Inc. Coprocessor interface controller
US20070294559A1 (en) * 2004-10-25 2007-12-20 Thomas Kottke Method and Device for Delaying Access to Data and/or Instructions of a Multiprocessor System
US20080163035A1 (en) * 2004-10-25 2008-07-03 Robert Bosch Gmbh Method for Data Distribution and Data Distribution Unit in a Multiprocessor System
JP3897046B2 (ja) * 2005-01-28 2007-03-22 横河電機株式会社 情報処理装置および情報処理方法
US20070038849A1 (en) * 2005-08-11 2007-02-15 Rajiv Madampath Computing system and method
US20090177866A1 (en) * 2008-01-08 2009-07-09 Choate Michael L System and method for functionally redundant computing system having a configurable delay between logically synchronized processors
US8819485B2 (en) * 2012-03-12 2014-08-26 Infineon Technologies Ag Method and system for fault containment
CN102970029A (zh) * 2012-11-06 2013-03-13 北京广利核系统工程有限公司 一种高安全性数字量信号采集电路
US9912754B2 (en) * 2015-05-01 2018-03-06 GM Global Technology Operations LLC Vehicular data isolation device
US10002056B2 (en) 2015-09-15 2018-06-19 Texas Instruments Incorporated Integrated circuit chip with cores asymmetrically oriented with respect to each other
US10740167B2 (en) * 2016-12-07 2020-08-11 Electronics And Telecommunications Research Institute Multi-core processor and cache management method thereof
CN110175091B (zh) * 2018-12-11 2023-06-23 中国航空工业集团公司西安航空计算技术研究所 一种Lockstep架构下的节点间信号同步方法、装置及电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2644205A1 (de) * 1976-09-30 1978-04-06 Agfa Gevaert Ag Fotografische kamera mit einer digitalen belichtungsregelvorrichtung
SE397013B (sv) * 1976-12-17 1977-10-10 Ellemtel Utvecklings Ab Sett och anordning for att overfora datainformationer till tva parallellt arbetande datamaskindelar
US4358823A (en) * 1977-03-25 1982-11-09 Trw, Inc. Double redundant processor
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
US4540898A (en) * 1983-03-07 1985-09-10 Motorola, Inc. Clocked buffer circuit using a self-bootstrapping transistor
US5231640A (en) * 1990-07-20 1993-07-27 Unisys Corporation Fault tolerant processor/memory architecture
DE69227956T2 (de) * 1991-07-18 1999-06-10 Tandem Computers Inc Multiprozessorsystem mit gespiegeltem Speicher
JPH05128080A (ja) * 1991-10-14 1993-05-25 Mitsubishi Electric Corp 情報処理装置
US5604754A (en) * 1995-02-27 1997-02-18 International Business Machines Corporation Validating the synchronization of lock step operated circuits
GB2317032A (en) * 1996-09-07 1998-03-11 Motorola Gmbh Microprocessor fail-safe system

Also Published As

Publication number Publication date
GB9817598D0 (en) 1998-10-07
DE69908717T2 (de) 2003-12-11
EP0980040B1 (en) 2003-06-11
ES2199527T3 (es) 2004-02-16
GB2340627A (en) 2000-02-23
CN1154944C (zh) 2004-06-23
CN1248748A (zh) 2000-03-29
RU99118019A (ru) 2001-08-27
EP0980040A3 (en) 2000-08-09
EP0980040A2 (en) 2000-02-16
US6519710B1 (en) 2003-02-11
GB2340627B (en) 2000-10-04
DE69908717D1 (de) 2003-07-17

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20080813