GR1006606B - Αρχιτεκτονικη διορθωσης μνημων με τεχνικη αμεσης απεικονισης - Google Patents

Αρχιτεκτονικη διορθωσης μνημων με τεχνικη αμεσης απεικονισης

Info

Publication number
GR1006606B
GR1006606B GR20080100449A GR20080100449A GR1006606B GR 1006606 B GR1006606 B GR 1006606B GR 20080100449 A GR20080100449 A GR 20080100449A GR 20080100449 A GR20080100449 A GR 20080100449A GR 1006606 B GR1006606 B GR 1006606B
Authority
GR
Greece
Prior art keywords
memory
word
corrective
defective
section
Prior art date
Application number
GR20080100449A
Other languages
English (en)
Inventor
Νικολαος Αξελος
Κιαμαλ Πεκμεστζης
Original Assignee
Νικολαος Αξελος
Κιαμαλ Πεκμεστζης
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Νικολαος Αξελος, Κιαμαλ Πεκμεστζης filed Critical Νικολαος Αξελος
Priority to GR20080100449A priority Critical patent/GR1006606B/el
Publication of GR1006606B publication Critical patent/GR1006606B/el

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory

Abstract

Διορθωτική μνήμη στην οποία απεικονίζονται ελαττωματικά κελιά μιας μνήμης πρός διόρθωση ΜΔ (62). Χρησιμοποιείται τεχνική άμεσης απεικόνισης για ταχύτητα και απλούστευση των κυκλωμάτων υποστήριξης. Η χωρητικότητα της διορθωτικής μνήμης εξαρτάται από το μέσο αναμενόμενο αριθμό ελαττωματικών κελιών της μνήμης πρός διόρθωση και εξοικονομείται κυκλωματική επιφάνεια σε σύγκριση με τις υπάρχουσες τεχνικές διόρθωσης μνημών. Αποτελείται από μία ή περισσότερες τράπεζες διορθωτικής μνήμης (63), με λέξεις που περιέχουν κατάλληλα δαιμορφωμένους δείκτες σηματοδότησης (flag) (66), σελιδοποίησης (tag) (65 )και τμήματος λέξης (pos) (70) που οδηγούν κυκλώμτα σύγκρισης και επίτρεψης (67), κυκλώματα επιλογής τμήματος (71) και κύκλωμα πολυπλεξίας (73). Σε περίπτωση επιλογής ελαττωματικής λέξης ή τμήματος λέξης της ΜΔ, το κύκλωμα πολυπλεξίας επιτρέπει τη σύνδεση μίας τράπεζας διορθωτικής μνήμης στο δίαυλο δεδομένων που αναλαμβάνει την αντικατάσταση της ελαττωματικής λέξης ή τμήματος λέξης της ΜΔ.
GR20080100449A 2008-07-04 2008-07-04 Αρχιτεκτονικη διορθωσης μνημων με τεχνικη αμεσης απεικονισης GR1006606B (el)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GR20080100449A GR1006606B (el) 2008-07-04 2008-07-04 Αρχιτεκτονικη διορθωσης μνημων με τεχνικη αμεσης απεικονισης

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GR20080100449A GR1006606B (el) 2008-07-04 2008-07-04 Αρχιτεκτονικη διορθωσης μνημων με τεχνικη αμεσης απεικονισης

Publications (1)

Publication Number Publication Date
GR1006606B true GR1006606B (el) 2009-11-20

Family

ID=40600379

Family Applications (1)

Application Number Title Priority Date Filing Date
GR20080100449A GR1006606B (el) 2008-07-04 2008-07-04 Αρχιτεκτονικη διορθωσης μνημων με τεχνικη αμεσης απεικονισης

Country Status (1)

Country Link
GR (1) GR1006606B (el)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994022085A1 (en) * 1993-03-19 1994-09-29 Memory Limited Fault tolerant memory system
WO1996031825A1 (en) * 1995-04-04 1996-10-10 Memory Corporation Plc Memory management
US6205065B1 (en) * 1999-01-26 2001-03-20 Nec Corporation Semiconductor memory device having redundancy memory circuit
US20010044916A1 (en) * 1998-08-28 2001-11-22 Blodgett Greg A. Device and method for repairing a semiconductor memory
US20050081093A1 (en) * 2003-09-29 2005-04-14 Joly Craig Shannon Ternary content addressable memory directed associative redundancy for semiconductor memories

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994022085A1 (en) * 1993-03-19 1994-09-29 Memory Limited Fault tolerant memory system
WO1996031825A1 (en) * 1995-04-04 1996-10-10 Memory Corporation Plc Memory management
US20010044916A1 (en) * 1998-08-28 2001-11-22 Blodgett Greg A. Device and method for repairing a semiconductor memory
US6205065B1 (en) * 1999-01-26 2001-03-20 Nec Corporation Semiconductor memory device having redundancy memory circuit
US20050081093A1 (en) * 2003-09-29 2005-04-14 Joly Craig Shannon Ternary content addressable memory directed associative redundancy for semiconductor memories

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PG Patent granted
ML Lapse due to non-payment of fees

Effective date: 20130104