GB995150A - Circuit arrangements for detecting and registering electrical pulses - Google Patents

Abstract

995,150. Automatic exchange systems. SIEMENS & HASLKE A.G. April 30, 1962 [April 28, 1961], No. 16333/62. Heading H4K. In a system in which pulses on metering wires set bi-stable elements (magnetic cores) which are subsequently read out by scanning pulses for transfer to a counter, and in which the metering pulses may be distorted (e.g. due to contact bounce), the scanning pulses are sufficiently frequent that at least one such pulse falls within an interval between the metering pulses during which none of the distortions are present, and feeding of a pulse to the counter only takes place provided a predetermined sequence of results is obtained from the scanning pulses. First embodiment, Figs. 1, 1a. Each metering wire is arranged to set one of cores K 11 , K xy of the matrix ZSP to condition " 1 " when it receives a pulse. Read-out is effected under control of the scanner TVZ, one row at a time, into a store AR comprising a core for each column, read-out restoring the core to condition " 0." These cores are read out successively under control of the scanner TVS. The main store SP, besides containing the accumulated meter totals for the lines also contains for each line a reference bit for indicating whether the last read-out for the line was 0 or 1. The circuit shown is for the case where the store SP records the information in serial form, the gate G 2 being arranged to accept the reference bit and the adder AD to accept the running total for the line. Each time one of the cores AR is read the corresponding information for the line is read out of the store SP. The circuit is arranged so that 1 is added to the total in SP only if successive readings for a line are 1 and 0. If the read-out from the store AR is a 1 and corresponding reference bit is 0, nothing is fed to the adder AD, but 1 is written into the reference bit via terminal a 2 . If the read-out from store and the reference bit are both 0 or both 1 nothing happens. If the read-out from the store is 0 and from the reference bit is 1, 1 is fed to the adder AD whose new total is fed back to SP via G 1 , and a pulse is sent via a 3 to cancel the reference bit in the store SP. Fig. la illustrates the timing sequences in the first embodiment. The top line indicates the metering pulses (a metering signal being " 1 ") including contact vibrations. The core fed by these signals remains in the " 1 " condition even during these vibrations and when reset by an enquiry pulse reverts to the "1" condition (after its termination and remains so set until an enquiry pulse occurs during a period in which the signals are not present. During this latter period (t p -i min ) two enquiry pulses are necessary in order to produce the required "1"- " 0 " result (i.e. the first resets the core and produces the " 1 " and the second now produces a " 0 "). Thus in the nomenclature of the Fig. 2 F ab #(tp-i min ). The arrangement may be modified by feeding the outputs of AR to a shift register which reads out the previous result, whereby the sequence " 1 "-" 0 " may be immediately detected to cause 1 to be added to the total, the store SP then not being required to store a reference bit. In a second embodiment, Fig. 2a, two closely spaced pulses a, b are used as enquiry pulses these being arranged so that one such pair must occur in each period F ab . The interval between the pulses a, b must. be sufficiently large that both pulses cannot fall within the pause (t p - prel ) between two contact bounces. The results of these enquiries are stored in separate stores and these results together with the read-out reference bit produce the following results:-If the reference bit reads out "0," any enquiry resulting in a " 1 " from pulse b causes a reference bit to be written in. An a-b sequence of " 1 "-" 0 " causes the addition of 1. If the reference bit reads out " 1 " and the result from an a pulse is " 0 " then 1 is added to the total. An a-b sequence " 1 "-" 0 " causes the cancellation of the reference bit. With this arrangement lines can be scanned at twice the rate of the previous arrangement.