GB990564A - Electronic counting circuits - Google Patents

Abstract

990,564. Selective signalling systems. HEWLETT-PACKARD CO. Sept. 18, 1962, No. 35577/62. Heading G4H. [Also in Division H3] To measure accurately the number of clock pulse periods in a given time period the partial pulse periods at the beginning and end are expanded in time and used to alter the integral number of pulses counted. As shown in Fig. 1 the beginning and end of the given time period may occur at or between pulse peaks so that measurement of the times 5, 6 is necessary. In the latter case this is achieved by measuring time 7 and taking its complement. Timer 9 applies a start pulse to lead 12 to cut off normally-conducting transistor 15 until the occurrence of the next clock pulse on terminals 10. A time-delay expander 35 comprises a one-shot asymmetrical oscillator in which the time taken to charge capacitor 23 in the one sense is multiplied by a factor of say 10 to charge the capacitor in the opposite sense. The time 5 results in a tenfold duration of potential at terminal 33. Gate 41 therefore applies an appropriate number of clock pulses to a binary-coded decimal counter 43. Meanwhile complete clock pulses are entered through 37 to advance the main counter 39, the first pulse being ignored. At the end of the prescribed time a stop signal on lead 14 operates a like time delay expander 47 the resulting count being complemented before application to counter 43. One or more carries may be made to the counter 39 via gate 45, the residue in 43 giving the first decimal place of the count.