GB985945A - Improvements in or relating to electrical signal limiting and amplifying circuits - Google Patents

Abstract

985,945. Transistor pulse squaring circuits. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. May 28, 1963 [May 28, 1962], No. 20474/62. Heading H3T. An amplifier-limiter comprises a pair of transistors X2, X3 having their emitters coupled by a capacitor C5 and separate emitter resistors R7, R9 through which substantially equal currents are arranged to flow under all signal conditions, the signal waveform being applied to the base of one of the transistors X2, for example through a grounded base buffer amplifier X1 (Fig. 1). Negative excursions of the signal cut-off transistor X3 and the capacitor C5 receivers a charge which is of the same value as when positive excursions of the signal cut-off transistor X2. The output waveform from transistor X3 then has an equal time spent on positive and negative voltage levels. The collector of transistor X3 is directly coupled to the base of transistor X4 and transistors X4, X5 have a similar action to transistors X2, X3. The output of the circuit is taken from an emitter follower X6. In Fig. 2 (not shown), the signal excursions fed to the bases of transistors X2 and X4 are limited by a capacitor in series with a pair of clipping diodes and Fig. 3 (not shown) includes additional biasing networks for the diodes to overcome the problem caused by the leakage current of the capacitors. Fig. 4 shows a transformer TR coupled emitter follower X1 feeding the bases of transistors X2, X3 in push-pull and the outputs of this pair feed a similar pair X4, X5.