GB971206A - Improvements in data transmission systems - Google Patents

Abstract

971, 206. Error correction. J. E. MEGGITT. Nov. 11, 1960 [Nov. 13, 1959; Aug. 4, 1960],Nos. 38602/59 and 27013/60. Heading G4A. Check digits are developed from a feed-back shift register and an adder according to a code defined by where T is a k x k matrix defined by the characteristic equation T<SP>n</SP> = 1; x is an arbitrary k x 1 vector; and the a's are the digits of a block of n - k data digits and k check digits. A feed back shift register is one in which selected stages are connected back to the input through an adder. The result of shifting the register is equivalent to applying a transformation T to the contents. If T defines a code of the kind required-then so does T<SP>-1</SP> since only the suffices of the a's are changed in the first equation. In the binary case C o is then 1. An encoder is shown in Fig. 1. The connections of the feed-back register are determined by the C's. If a C is 0 there is no connection. C o is always 1. The n-k data bits are received on line 13. Switch S 2 is initially closed so that the bits pass through the mod 2 adder 12. Switch S 1 is connected to the snift register 11. The outputs of the register are combined in the adder 12 to give expression to the first equation, with T replaced by T<SP>-1</SP>, and when all the data bits have been received switch S 2 is opened and switch S 1 connected to line 13 for transmission of the block of k check bits. In decoding there is computed where the a<SP>1</SP> are the received digits. If z = 0 the message has been received correctly and if z is, non-zero it shows within predetermined limits the number and kind of errors. Fig. 2 shows a decoder. The received data is operated on by the register 16 and adder 17 is the same way as in the decoder. Circuit 18 is designed to emit 1 when the pattern in register 16 is of a particular form. The received message is delayed in shift register 19 while the calculation is proceeding. When z has been calculated the register 16 is recirculated. When a pattern associated with an error in a particular bit is detected the bit will be in adder 20. The 1 emitted by circuit 18 will complement the bit and correct the error. The theory is explained in the Specification and examples of particular decoders are given. Where all errors occurring in bursts of up to x bits are to be detected, the output of register 16 is split into two parts and summed mod 2. The first adder receives the outputs of stages k-1 to x 1 and the second adder the outputs of stages x-1 to 0. When the first adder contains zero and the second adder contains 1, an error is detected. An extension of the theory to fields of 4, 8 or 16 elements is briefly outlined.