GB9522469D0 - Memory device with address decoder - Google Patents
Memory device with address decoderInfo
- Publication number
- GB9522469D0 GB9522469D0 GBGB9522469.7A GB9522469A GB9522469D0 GB 9522469 D0 GB9522469 D0 GB 9522469D0 GB 9522469 A GB9522469 A GB 9522469A GB 9522469 D0 GB9522469 D0 GB 9522469D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory device
- address decoder
- decoder
- address
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33560694A | 1994-11-08 | 1994-11-08 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9522469D0 true GB9522469D0 (en) | 1996-01-03 |
GB2295036A GB2295036A (en) | 1996-05-15 |
GB2295036B GB2295036B (en) | 1999-01-27 |
Family
ID=23312483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9522469A Expired - Fee Related GB2295036B (en) | 1994-11-08 | 1995-11-02 | Memory device with address decoder |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP3694554B2 (en) |
DE (1) | DE19538994C2 (en) |
GB (1) | GB2295036B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6047352A (en) | 1996-10-29 | 2000-04-04 | Micron Technology, Inc. | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure |
DE19929172B4 (en) * | 1999-06-25 | 2006-12-28 | Infineon Technologies Ag | Integrated memory |
-
1995
- 1995-10-19 DE DE1995138994 patent/DE19538994C2/en not_active Expired - Fee Related
- 1995-11-02 GB GB9522469A patent/GB2295036B/en not_active Expired - Fee Related
- 1995-11-08 JP JP31476995A patent/JP3694554B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE19538994A1 (en) | 1996-05-09 |
GB2295036A (en) | 1996-05-15 |
JP3694554B2 (en) | 2005-09-14 |
DE19538994C2 (en) | 1998-04-16 |
GB2295036B (en) | 1999-01-27 |
JPH08235868A (en) | 1996-09-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2317721B (en) | Memory device | |
GB2317722B (en) | Memory device | |
IL122052A0 (en) | Memory device | |
EP0720171A3 (en) | Ferroelectric memory device | |
GB9606928D0 (en) | Memory devices | |
GB9620370D0 (en) | Memory device | |
HK1018564A1 (en) | Inverse transport processor with memory address circuitry | |
IL121044A (en) | Dynamic memory device | |
GB9605873D0 (en) | Memory device | |
SG70015A1 (en) | Inverse transport processor with memory address circuitry | |
GB9613088D0 (en) | Memory device | |
GB9609833D0 (en) | Memory device | |
GB9417264D0 (en) | Memory device | |
GB2289777B (en) | Memory device with page select capability | |
KR0132636B1 (en) | Memory device | |
GB9421138D0 (en) | Memory device | |
EP0872847A4 (en) | Memory | |
GB9408901D0 (en) | Serial access memory device | |
EP0704805A3 (en) | Address translation device | |
GB9417271D0 (en) | Memory device | |
GB2310062B (en) | Memory device | |
GB9521977D0 (en) | Cache memory | |
GB2283128B (en) | Memory device | |
GB2295036B (en) | Memory device with address decoder | |
SG73484A1 (en) | Address decoder semiconductor memory and semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19991102 |