GB9503964D0 - Method and apparatus for interfacing with ram - Google Patents

Method and apparatus for interfacing with ram

Info

Publication number
GB9503964D0
GB9503964D0 GBGB9503964.0A GB9503964A GB9503964D0 GB 9503964 D0 GB9503964 D0 GB 9503964D0 GB 9503964 A GB9503964 A GB 9503964A GB 9503964 D0 GB9503964 D0 GB 9503964D0
Authority
GB
United Kingdom
Prior art keywords
interfacing
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB9503964.0A
Other versions
GB2287808A (en
GB2287808B (en
Inventor
Anthony Mark Jones
Donald William W Patterson
William Philip Robbins
Adrian Philip Wise
Helen Rosemary Finch
Martin William Sotheran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Discovision Associates
Original Assignee
Discovision Associates
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9405914A external-priority patent/GB9405914D0/en
Priority claimed from GB9415413A external-priority patent/GB9415413D0/en
Priority claimed from GB9415387A external-priority patent/GB9415387D0/en
Priority claimed from GB9415365A external-priority patent/GB9415365D0/en
Priority claimed from GB9415391A external-priority patent/GB9415391D0/en
Priority to GB9503964A priority Critical patent/GB2287808B/en
Application filed by Discovision Associates filed Critical Discovision Associates
Priority to CA002145363A priority patent/CA2145363C/en
Priority to CA002145365A priority patent/CA2145365C/en
Priority to CA002244810A priority patent/CA2244810A1/en
Priority to KR1019950006173A priority patent/KR100275427B1/en
Priority to CA002145362A priority patent/CA2145362A1/en
Priority to CA002145379A priority patent/CA2145379C/en
Priority to CA002145361A priority patent/CA2145361C/en
Priority to JP7090019A priority patent/JPH0855060A/en
Priority to CN95104511.3A priority patent/CN1118475A/en
Publication of GB9503964D0 publication Critical patent/GB9503964D0/en
Priority to US08/474,603 priority patent/US5861894A/en
Priority to US08/473,868 priority patent/US5761741A/en
Priority to US08/474,220 priority patent/US5699544A/en
Priority to US08/474,231 priority patent/US6018354A/en
Priority to JP7202793A priority patent/JPH08179984A/en
Priority to JP20269195A priority patent/JP3741464B2/en
Priority to JP7202752A priority patent/JPH08241066A/en
Priority to JP7202744A priority patent/JPH08179983A/en
Publication of GB2287808A publication Critical patent/GB2287808A/en
Priority to US08/812,820 priority patent/US5724537A/en
Priority to US08/876,720 priority patent/US6034674A/en
Priority to US08/950,892 priority patent/US5956741A/en
Publication of GB2287808B publication Critical patent/GB2287808B/en
Application granted granted Critical
Priority to US09/325,691 priority patent/US6297857B1/en
Priority to US09/323,627 priority patent/US6417859B1/en
Priority to US09/330,795 priority patent/US6378030B1/en
Priority to JP2000288305A priority patent/JP2001128108A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
GB9503964A 1992-06-30 1995-02-28 Method and apparatus for interfacing with ram Expired - Fee Related GB2287808B (en)

Priority Applications (25)

Application Number Priority Date Filing Date Title
GB9503964A GB2287808B (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram
CA002145361A CA2145361C (en) 1994-03-24 1995-03-23 Buffer manager
CA002145363A CA2145363C (en) 1994-03-24 1995-03-23 Ram interface
CA002145379A CA2145379C (en) 1994-03-24 1995-03-23 Method and apparatus for addressing memory
CA002145362A CA2145362A1 (en) 1994-03-24 1995-03-23 Method for accessing ram
KR1019950006173A KR100275427B1 (en) 1994-03-24 1995-03-23 Method and apparatus for interfacing with ram
CA002145365A CA2145365C (en) 1994-03-24 1995-03-23 Method for accessing banks of dram
CA002244810A CA2244810A1 (en) 1994-03-24 1995-03-23 Method for addressing memory
JP7090019A JPH0855060A (en) 1994-03-24 1995-03-24 Ram access method
CN95104511.3A CN1118475A (en) 1994-03-24 1995-03-24 Method and apparatus for interfacing with RAM
US08/473,868 US5761741A (en) 1994-03-24 1995-06-07 Technique for addressing a partial word and concurrently providing a substitution field
US08/474,220 US5699544A (en) 1993-06-24 1995-06-07 Method and apparatus for using a fixed width word for addressing variable width data
US08/474,231 US6018354A (en) 1994-03-24 1995-06-07 Method for accessing banks of DRAM
US08/474,603 US5861894A (en) 1993-06-24 1995-06-07 Buffer manager
JP7202793A JPH08179984A (en) 1994-03-24 1995-07-18 Processing method for addressing of memory
JP20269195A JP3741464B2 (en) 1994-03-24 1995-07-18 DRAM access method
JP7202752A JPH08241066A (en) 1994-03-24 1995-07-18 Method for control of buffering
JP7202744A JPH08179983A (en) 1994-03-24 1995-07-18 Ram interface device
US08/812,820 US5724537A (en) 1994-03-24 1997-03-06 Interface for connecting a bus to a random access memory using a two wire link
US08/876,720 US6034674A (en) 1992-06-30 1997-06-16 Buffer manager
US08/950,892 US5956741A (en) 1994-03-24 1997-10-15 Interface for connecting a bus to a random access memory using a swing buffer and a buffer manager
US09/323,627 US6417859B1 (en) 1992-06-30 1999-06-01 Method and apparatus for displaying video data
US09/325,691 US6297857B1 (en) 1994-03-24 1999-06-01 Method for accessing banks of DRAM
US09/330,795 US6378030B1 (en) 1994-03-24 1999-06-14 Method and apparatus for processing video data
JP2000288305A JP2001128108A (en) 1994-03-24 2000-09-22 Video processor

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB9405914A GB9405914D0 (en) 1994-03-24 1994-03-24 Video decompression
GB9415365A GB9415365D0 (en) 1994-07-29 1994-07-29 Method for accessing ram
GB9415391A GB9415391D0 (en) 1994-07-29 1994-07-29 Method for accessing banks of dram
GB9415413A GB9415413D0 (en) 1994-07-29 1994-07-29 Method and apparatus for video decompression
GB9415387A GB9415387D0 (en) 1994-07-29 1994-07-29 Method and apparatus for addressing memory
GB9503964A GB2287808B (en) 1994-03-24 1995-02-28 Method and apparatus for interfacing with ram

Publications (3)

Publication Number Publication Date
GB9503964D0 true GB9503964D0 (en) 1995-04-19
GB2287808A GB2287808A (en) 1995-09-27
GB2287808B GB2287808B (en) 1998-08-05

Family

ID=27547221

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9503964A Expired - Fee Related GB2287808B (en) 1992-06-30 1995-02-28 Method and apparatus for interfacing with ram

Country Status (1)

Country Link
GB (1) GB2287808B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2368696B (en) * 2000-11-02 2005-03-02 Sunplus Technology Co Ltd Architecture for video decompresor to efficiently access synchronously memory
US20050144369A1 (en) * 2002-02-06 2005-06-30 Koninklijke Philips Electronics N.V. Address space, bus system, memory controller and device system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100214435B1 (en) * 1990-07-25 1999-08-02 사와무라 시코 Synchronous burst-access memory

Also Published As

Publication number Publication date
GB2287808A (en) 1995-09-27
GB2287808B (en) 1998-08-05

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20100408 AND 20100414

732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20130221 AND 20130227

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20130228