CA2145362A1 - Method for accessing ram - Google Patents
Method for accessing ramInfo
- Publication number
- CA2145362A1 CA2145362A1 CA002145362A CA2145362A CA2145362A1 CA 2145362 A1 CA2145362 A1 CA 2145362A1 CA 002145362 A CA002145362 A CA 002145362A CA 2145362 A CA2145362 A CA 2145362A CA 2145362 A1 CA2145362 A1 CA 2145362A1
- Authority
- CA
- Canada
- Prior art keywords
- ram
- read
- words
- written
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Landscapes
- Dram (AREA)
Abstract
The present invention is directed to a method of accessing from RAM a number M of words that is less than the predetermined fixed burst length N of the RAM. The RAM includes an enable line that selectably enables and disables reading from and writing to the RAM. In the method, first N words are ordered to be read from or written to the RAM. Next it is determined when M words have been read from or written to the RAM, M being less than N.
Finally, the RAM is disabled upon determining M words had been read from or written to the RAM.
Finally, the RAM is disabled upon determining M words had been read from or written to the RAM.
Description
`~ ~ 2~362 METHOD FOR ACCESSING RAM
REFERENCE TO RELATED APPLICATIONS
Thls applicatlon ls related to Brltlsh Patent Appllcatlon entltled "Method for Accesslng RAM" as U.K. Serlal No. 9415365.7 flled on July 29, 1994 and Brltlsh Patent Appllcatlon entltled "Vldeo Decompresslon" as U.K. Serlal No.
9405914.4 flled on March 24, 1994 and Brltlsh Patent Appllcatlon entltled "Method and Apparatus for Interfaclng wlth RAM" as U.K. Serlal No. 9503964.0 flled on February 28, 1995.
BACKGROUND
The present lnventlon relates to random access memory (RAM), and more partlcularly, to a method for accesslng synchronous dynamlc RAM.
There are a number of approaches to lmplementlng the next generatlon of hlgh speed data bus. Three popular approaches are the RAMBUS, the INTERBUS, and buses based on synchronous DRAM. Of the synchronous DRAM approaches, one approach that ls llkely to become popular ls that governed by a JEDEC standard.
The JEDEC standard has a number of features that warrant mentlonlng. Some of these features are falrly straight-forward. Under the JEDEC standard, data ls lnterleaved between two banks, data can be wrltten ln burst lengths of two, four, elght, or more, and each CAS (column address strobe) can generate more than one column address 21~S3~2 lnternal to the synchronous DRAM (a feature that aids page mode addresslng). Eight cycles are required to precharge, in which time eight reads or writes could be performed.
The JEDEC standard also sets some rules that are not intuitively necessary or even desirable. The following three rules deserve particular attention 1) Only an even number of data words can be accessed (i.e., read from or written to the DRAM).
REFERENCE TO RELATED APPLICATIONS
Thls applicatlon ls related to Brltlsh Patent Appllcatlon entltled "Method for Accesslng RAM" as U.K. Serlal No. 9415365.7 flled on July 29, 1994 and Brltlsh Patent Appllcatlon entltled "Vldeo Decompresslon" as U.K. Serlal No.
9405914.4 flled on March 24, 1994 and Brltlsh Patent Appllcatlon entltled "Method and Apparatus for Interfaclng wlth RAM" as U.K. Serlal No. 9503964.0 flled on February 28, 1995.
BACKGROUND
The present lnventlon relates to random access memory (RAM), and more partlcularly, to a method for accesslng synchronous dynamlc RAM.
There are a number of approaches to lmplementlng the next generatlon of hlgh speed data bus. Three popular approaches are the RAMBUS, the INTERBUS, and buses based on synchronous DRAM. Of the synchronous DRAM approaches, one approach that ls llkely to become popular ls that governed by a JEDEC standard.
The JEDEC standard has a number of features that warrant mentlonlng. Some of these features are falrly straight-forward. Under the JEDEC standard, data ls lnterleaved between two banks, data can be wrltten ln burst lengths of two, four, elght, or more, and each CAS (column address strobe) can generate more than one column address 21~S3~2 lnternal to the synchronous DRAM (a feature that aids page mode addresslng). Eight cycles are required to precharge, in which time eight reads or writes could be performed.
The JEDEC standard also sets some rules that are not intuitively necessary or even desirable. The following three rules deserve particular attention 1) Only an even number of data words can be accessed (i.e., read from or written to the DRAM).
2) The minimum number of data words that can be accessed at a tlme ls two.
3) The internal row counter "toggles" bits, rather than actually countlng, thus data words can only be accessed from an even count.
The JEDEC standard speclfles many low-level commands, but the following seven low-level commands are sufficient for most applicatlons: actlve; read; wrlte;
refresh, read and precharge; write and precharge; and NOP. In actual practlce, uslng these seven commands to effectlvely and efficiently access DRAM is a difficult task, partlcularly in llght of the rules llsted above. There is therefore a need for a structured and slmple methodology for accesslng the synchronous DRAM ln the most efflclent manner, whllst adherlng to the JEDEC rules.
SUMMARY OF THE INVENTION
The present lnventlon ls dlrected to a method for 2l~362 accessing RAM. In partlcular, the method of the invention accesses from a RAM a number M of words that is less than the predetermined fixed burst length N of the RAM. The RAM
includes an enable line that selectably enables and disables reading from and writing to the RAM. In the method, first N
words are ordered to be read from or written to the RAM. Next it is determined when M words have been read from or written to the RAM, M being less than N. Finally, the RAM is disabled upon determining M words had been read from or written to the RAM.
BRIEF DESCRIPTION OF THE DRAWING
Figure 1 is a system block diagram of an apparatus that employs the method of the present invention to access a synchronous DRAM.
Figure 2 is a diagram of the interrelation between the high level commands received, and the low level commands generated, by the state machine of figure 1.
Figure 3 ls a pictorial representation of the organization of the DRAM of figure 1.
Figure 4 is a plctorial representatlon of the organization of words stored in cells in the DRAM of figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to figure 1, there is shown a block diagram of a system 10 for implementing the method of the present invention. System 10 includes state machine 12, interleaver 14, and synchronous DRAM 16. DRAM 16 includes two 21~36~
banks 32. Interleaver 14 controls access (e.g., read and wrlte~ to DRAM 16. Interleaver 14 includes counter (not shown) that tracks which bank 32 was most recently accessed, allowing interleaver 14 to easily toggle between banks 32.
Referring now to figures 1, 2, and 3, upon receipt of a string 19 of high level commands 22 addressed to the same bank 32 of DRAM 16, state machine 12 generates a string 21 of optimized low-level commands 20 (l.e., the seven commands specified by JEDEC, and listed above) addressed to the same bank 32. Upon receipt of string 21, lnterleaver 14 performs the requested actions.
High level commands 22 are READ 22-1, WRITE 22-2, EXTEND 22-3, INTERRUPT 22-4 and REFRESH 22-5. ~Commands 22 are printed in all capital letters to readlly dlstinguish them from low-level commands 20.) In brief, the operation of READ
22-1, WRITE 22-2 and REFRESH 22-5 commands is essentially the same as their low-level command 20 namesakes. EXTEND 22-3 acts to repeat the actions of the previous WRITE 22-2 or READ
22-1 command. INTERRUPT 22-4 is needed as a result of the burst length being fixed at four words 24, as discussed further below. Taken together, commands 22 provide a powerful programming tool.
~ efore studying examples of how commands 22 simplify the task of accessing DRAM 16, commands 22 themselves should be examlned in more detail. The first hlgh-level command 22 of hlgh-level command string 19 is either READ 22-1 or WRITE
22-2. The first low-level command 20 of the corresponding low-level command string 21 is always active command 20. Each 2 1 ~ 2 -READ or WRITE command 22 orders four sequential words 24 to be read or wrltten, respectlvely. As shown ln flgure 2, each READ or WRITE command 22 ls accompanied by the address 26 (in the particular bank 32 belng accessed) of the flrst word 24 of the four sequentlal words 24. (Note that under the JEDEC
standard, thls flrst word 24 must be an even count.) When DRAM 16 is ln "automatlc precharge mode," if the READ or WRITE command 22 is the last command 22 ln strlng 19 (l.e., lf the next command to state machlne 12 ls addressed to the other bank 32 of DRAM 16~, then state machlne 12 wlll lssue a read or write with precharge command 20, followed by the requisite addresses 26 of the appropriate four sequentlal words 24. Otherwlse, state machine 12 wlll generate a read or wrlte command 20, followed by the requlslte addresses 26. For example, lf ln automatlc precharge mode the last command 22 in strlng 19-2 is READ 221 wlth address 26 of 10, the corresponding string 21-2 wlll be read wlth precharge command 20, followed by addresses 26 of 10, 11, 12 and 13.
In flgure 2, EXTEND 22-3 ls shown at the end of strlng 19-3, followlng READ (WRITE) command 22. Llke READ and WRITE commands 22, the format of EXTEND 22-3 includes the address 26 of the flrst word 24 in a sequence of four words 24. In the automatic precharge mode, when EXTEND 22-3 occurs at the end of a string 19, as ln strlng 19-3, an addltlonal read (wrlte) wlth precharge is added to strlng 21.
Another aspect of the lnventlon flxes the burst length at four words 24, savlng the complexlty needed to support a dynamlcally varylng burst length. To handle the two ` 21453~2 word transfers required by the JEDEC standard, INTERRUPT 22-4 is provided. Referring now to figure 1, 2 and 3, INTERRUPT
22-4 causes state machine 12 to begin a four word 24 long low-level command 20 read (or wrlte). However, after two words 24 have been read (or written), state machine 12 causes enable line 30 to banks 32 to go low, disabling banks 32. In this manner, although state machine 12 issues low level command 20 for a four word 24 read (or write), only two words 24 are actually read from (or written to) banks 32.
Of course, after enable line 30 is dropped low, another two clock cycles are required to complete the now ineffective read (or write) command 20. But this approach saves having to deal with two words 24 of unwanted data, while allowing the burst length to be fixed at four words 24.
Referring now to figures 1, 2, 3 and 4, in figure 4 there is a diagram portraying how words 24 are stored within banks 32. Figure 4 shows a portion 48 of a two dimensional array of cells 50, each cell 50 including an M by N matrix of words 24, each word being represented by a number 54 that serves as the address of the word 24 within the cell 50. In particular, each cell 50 is shown as being eight rows by eight colums of words 24. Cells 50 are aligned according to grid pattern 56.
Superlmposed on cells 50 is a cell 60 that represents a desired new cell to be created by reading words 24 from the underlying cells 50 (for storage in another portion of DRAM 16). Cell 60 is aligned with words 24, but that is not aligned with grid pattern 56. Cell 60 overlies cells 50-1, 50-2, 50-3 and 50-4. Cells 50-1 and 50-3 contaln words 24 stored ln the same bank 32 (e.g., bankO), but possibly on different pages. Similarly, cells 50-2 and 50-4 contain words 24 stored in the other bank 32 (e.g., bankl), but possibly on different pages.
To read the appropriate words 24 from cell 50-1, one could use the following string 19 of high-level commands 22 READ(62,x), INTERRUPT(62,62).
The corresponding string 21 of low-level commands 20 would be:
active(bankO), read(62,63), read(62,63), read and precharge(62,63).
To read the appropriate words 24 from cell 50-4, one could use the following high-level commands 22:
READ(6,x), INTERRUPT(14,22).
The corresonding string 21 of low-level commands 20 would be active(bankO), read(6,7), read(14,15,don't care,don't care) read and precharge(22,23,don't care,don't care).
To read the appropriate words 24 from cell 50-3, one 0 could use the following high-level commands 22 READ(O,x), EXTEND(8,x), EXTEND(16,x), EXTEND(4,x), INTERRUPT(12,20).
The corresponding string 21 of low-level commands 20 would be active(bankO), read(O,1,2,3), read(8,9,10,11), read(16,17,18,19), read(4,5), read(12,13), read and precharge(20,21,don't care, don't care).
While the invention has been described wlth reference to the structures and methods disclosed, it ls not 2l45362 confined to the specific details set forth, but is intended to cover such modlficatlons or changes as may come wlthln the scope of the followlng claims.
The JEDEC standard speclfles many low-level commands, but the following seven low-level commands are sufficient for most applicatlons: actlve; read; wrlte;
refresh, read and precharge; write and precharge; and NOP. In actual practlce, uslng these seven commands to effectlvely and efficiently access DRAM is a difficult task, partlcularly in llght of the rules llsted above. There is therefore a need for a structured and slmple methodology for accesslng the synchronous DRAM ln the most efflclent manner, whllst adherlng to the JEDEC rules.
SUMMARY OF THE INVENTION
The present lnventlon ls dlrected to a method for 2l~362 accessing RAM. In partlcular, the method of the invention accesses from a RAM a number M of words that is less than the predetermined fixed burst length N of the RAM. The RAM
includes an enable line that selectably enables and disables reading from and writing to the RAM. In the method, first N
words are ordered to be read from or written to the RAM. Next it is determined when M words have been read from or written to the RAM, M being less than N. Finally, the RAM is disabled upon determining M words had been read from or written to the RAM.
BRIEF DESCRIPTION OF THE DRAWING
Figure 1 is a system block diagram of an apparatus that employs the method of the present invention to access a synchronous DRAM.
Figure 2 is a diagram of the interrelation between the high level commands received, and the low level commands generated, by the state machine of figure 1.
Figure 3 ls a pictorial representation of the organization of the DRAM of figure 1.
Figure 4 is a plctorial representatlon of the organization of words stored in cells in the DRAM of figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to figure 1, there is shown a block diagram of a system 10 for implementing the method of the present invention. System 10 includes state machine 12, interleaver 14, and synchronous DRAM 16. DRAM 16 includes two 21~36~
banks 32. Interleaver 14 controls access (e.g., read and wrlte~ to DRAM 16. Interleaver 14 includes counter (not shown) that tracks which bank 32 was most recently accessed, allowing interleaver 14 to easily toggle between banks 32.
Referring now to figures 1, 2, and 3, upon receipt of a string 19 of high level commands 22 addressed to the same bank 32 of DRAM 16, state machine 12 generates a string 21 of optimized low-level commands 20 (l.e., the seven commands specified by JEDEC, and listed above) addressed to the same bank 32. Upon receipt of string 21, lnterleaver 14 performs the requested actions.
High level commands 22 are READ 22-1, WRITE 22-2, EXTEND 22-3, INTERRUPT 22-4 and REFRESH 22-5. ~Commands 22 are printed in all capital letters to readlly dlstinguish them from low-level commands 20.) In brief, the operation of READ
22-1, WRITE 22-2 and REFRESH 22-5 commands is essentially the same as their low-level command 20 namesakes. EXTEND 22-3 acts to repeat the actions of the previous WRITE 22-2 or READ
22-1 command. INTERRUPT 22-4 is needed as a result of the burst length being fixed at four words 24, as discussed further below. Taken together, commands 22 provide a powerful programming tool.
~ efore studying examples of how commands 22 simplify the task of accessing DRAM 16, commands 22 themselves should be examlned in more detail. The first hlgh-level command 22 of hlgh-level command string 19 is either READ 22-1 or WRITE
22-2. The first low-level command 20 of the corresponding low-level command string 21 is always active command 20. Each 2 1 ~ 2 -READ or WRITE command 22 orders four sequential words 24 to be read or wrltten, respectlvely. As shown ln flgure 2, each READ or WRITE command 22 ls accompanied by the address 26 (in the particular bank 32 belng accessed) of the flrst word 24 of the four sequentlal words 24. (Note that under the JEDEC
standard, thls flrst word 24 must be an even count.) When DRAM 16 is ln "automatlc precharge mode," if the READ or WRITE command 22 is the last command 22 ln strlng 19 (l.e., lf the next command to state machlne 12 ls addressed to the other bank 32 of DRAM 16~, then state machlne 12 wlll lssue a read or write with precharge command 20, followed by the requisite addresses 26 of the appropriate four sequentlal words 24. Otherwlse, state machine 12 wlll generate a read or wrlte command 20, followed by the requlslte addresses 26. For example, lf ln automatlc precharge mode the last command 22 in strlng 19-2 is READ 221 wlth address 26 of 10, the corresponding string 21-2 wlll be read wlth precharge command 20, followed by addresses 26 of 10, 11, 12 and 13.
In flgure 2, EXTEND 22-3 ls shown at the end of strlng 19-3, followlng READ (WRITE) command 22. Llke READ and WRITE commands 22, the format of EXTEND 22-3 includes the address 26 of the flrst word 24 in a sequence of four words 24. In the automatic precharge mode, when EXTEND 22-3 occurs at the end of a string 19, as ln strlng 19-3, an addltlonal read (wrlte) wlth precharge is added to strlng 21.
Another aspect of the lnventlon flxes the burst length at four words 24, savlng the complexlty needed to support a dynamlcally varylng burst length. To handle the two ` 21453~2 word transfers required by the JEDEC standard, INTERRUPT 22-4 is provided. Referring now to figure 1, 2 and 3, INTERRUPT
22-4 causes state machine 12 to begin a four word 24 long low-level command 20 read (or wrlte). However, after two words 24 have been read (or written), state machine 12 causes enable line 30 to banks 32 to go low, disabling banks 32. In this manner, although state machine 12 issues low level command 20 for a four word 24 read (or write), only two words 24 are actually read from (or written to) banks 32.
Of course, after enable line 30 is dropped low, another two clock cycles are required to complete the now ineffective read (or write) command 20. But this approach saves having to deal with two words 24 of unwanted data, while allowing the burst length to be fixed at four words 24.
Referring now to figures 1, 2, 3 and 4, in figure 4 there is a diagram portraying how words 24 are stored within banks 32. Figure 4 shows a portion 48 of a two dimensional array of cells 50, each cell 50 including an M by N matrix of words 24, each word being represented by a number 54 that serves as the address of the word 24 within the cell 50. In particular, each cell 50 is shown as being eight rows by eight colums of words 24. Cells 50 are aligned according to grid pattern 56.
Superlmposed on cells 50 is a cell 60 that represents a desired new cell to be created by reading words 24 from the underlying cells 50 (for storage in another portion of DRAM 16). Cell 60 is aligned with words 24, but that is not aligned with grid pattern 56. Cell 60 overlies cells 50-1, 50-2, 50-3 and 50-4. Cells 50-1 and 50-3 contaln words 24 stored ln the same bank 32 (e.g., bankO), but possibly on different pages. Similarly, cells 50-2 and 50-4 contain words 24 stored in the other bank 32 (e.g., bankl), but possibly on different pages.
To read the appropriate words 24 from cell 50-1, one could use the following string 19 of high-level commands 22 READ(62,x), INTERRUPT(62,62).
The corresponding string 21 of low-level commands 20 would be:
active(bankO), read(62,63), read(62,63), read and precharge(62,63).
To read the appropriate words 24 from cell 50-4, one could use the following high-level commands 22:
READ(6,x), INTERRUPT(14,22).
The corresonding string 21 of low-level commands 20 would be active(bankO), read(6,7), read(14,15,don't care,don't care) read and precharge(22,23,don't care,don't care).
To read the appropriate words 24 from cell 50-3, one 0 could use the following high-level commands 22 READ(O,x), EXTEND(8,x), EXTEND(16,x), EXTEND(4,x), INTERRUPT(12,20).
The corresponding string 21 of low-level commands 20 would be active(bankO), read(O,1,2,3), read(8,9,10,11), read(16,17,18,19), read(4,5), read(12,13), read and precharge(20,21,don't care, don't care).
While the invention has been described wlth reference to the structures and methods disclosed, it ls not 2l45362 confined to the specific details set forth, but is intended to cover such modlficatlons or changes as may come wlthln the scope of the followlng claims.
Claims (3)
1. A method of accessing from RAM a number M of words that is less than the predetermined fixed burst length N of the RAM, the RAM including an enable line that selectably enables and disables reading from and writing to the RAM, the method comprising the steps of:
ordering N words to be read from or written to the RAM;
determining when M words have been read from or written to the RAM, M being less than N; and disabling the RAM upon determining M words had been read from or written to the RAM.
ordering N words to be read from or written to the RAM;
determining when M words have been read from or written to the RAM, M being less than N; and disabling the RAM upon determining M words had been read from or written to the RAM.
2. A method of reading from RAM a number M of words that is less than the predetermined fixed burst length N of the RAM, the RAM including an enable line that selectably enables and disables reading from the RAM, the method comprising the steps of ordering N words to be read from the RAM;
determining when M words have been read from the RAM, M
being less than N and disabling the RAM upon determining M words had been read from the RAM.
determining when M words have been read from the RAM, M
being less than N and disabling the RAM upon determining M words had been read from the RAM.
3. A method of writing to RAM a number M of words that is less than the predetermined fixed burst length N of the RAM, the RAM including an enable line that selectably enables and disables writing to the RAM, the method comprising the steps of:
ordering N words to be written to the RAM;
determining when M words have been written to the RAM, M
being less than N; and disabling the RAM upon determining M words had been written to the RAM.
ordering N words to be written to the RAM;
determining when M words have been written to the RAM, M
being less than N; and disabling the RAM upon determining M words had been written to the RAM.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9405914A GB9405914D0 (en) | 1994-03-24 | 1994-03-24 | Video decompression |
| GB9415365A GB9415365D0 (en) | 1994-07-29 | 1994-07-29 | Method for accessing ram |
| GB9405914.4 | 1995-02-28 | ||
| GB9415365.7 | 1995-02-28 | ||
| GB9503964A GB2287808B (en) | 1994-03-24 | 1995-02-28 | Method and apparatus for interfacing with ram |
| GB9503964.0 | 1995-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2145362A1 true CA2145362A1 (en) | 1995-09-25 |
Family
ID=27267119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002145362A Abandoned CA2145362A1 (en) | 1994-03-24 | 1995-03-23 | Method for accessing ram |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2145362A1 (en) |
-
1995
- 1995-03-23 CA CA002145362A patent/CA2145362A1/en not_active Abandoned
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4937791A (en) | High performance dynamic ram interface | |
| WO2001006371A1 (en) | Improved memory system apparatus and method | |
| US20060059320A1 (en) | Memory control device | |
| US6754135B2 (en) | Reduced latency wide-I/O burst architecture | |
| US7350018B2 (en) | Method and system for using dynamic random access memory as cache memory | |
| JP3786993B2 (en) | Data storage unit and data storage device using the unit | |
| EP1026600B1 (en) | Method and apparatus for interfacing with RAM | |
| US5949734A (en) | Semiconductor memory device | |
| US20040190362A1 (en) | Dram and access method | |
| CN102567243B (en) | Storage device and refreshing method for same | |
| US7543105B2 (en) | Memory access control based on hit prediction | |
| KR100607987B1 (en) | Memory controller for scheduling a plurality of commands, and method thereof | |
| KR100619202B1 (en) | Apparatus and method for encoding auto-precharge | |
| KR101022473B1 (en) | Memory bank interleaving method and apparatus in the multi-layer bus system | |
| CA2145362A1 (en) | Method for accessing ram | |
| JPH08328949A (en) | Storage device | |
| CN113113061A (en) | Memory device, memory module, and method of operating memory device | |
| US20210157495A1 (en) | Device and method for controlling data-reading and -writing | |
| US6141727A (en) | Device and method for controlling data storage device | |
| JP3314395B2 (en) | Memory controller | |
| KR950008663B1 (en) | Dram access control apparatus | |
| JPH04248641A (en) | Memory controller | |
| JPH05210572A (en) | Memory controller | |
| JP3655658B2 (en) | Numerical controller | |
| JPH0628869A (en) | Meory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |