GB939843A - Improvements in or relating to electric switching circuits - Google Patents

Abstract

939,843. Transistor logical circuits. COMPUTER DEVELOPMENTS Ltd. Jan. 29, 1960 [Feb. 25, 1959], No. 6520/59. Class 40 (6). [Also in Group XIX] A switching circuit comprises a network of at least four arms forming a closed loop, one of the arms comprising an output load and the other arms each comprising a voltage saturation device which is adapted to be saturated or not according to the state of a respective input switching current signal. The arrangement is such that the switching currents flow in the same direction with respect to the loop, and the voltage developed across the output load is less than a first predetermined level except when the sum of the saturation voltages of the devices supplied with an input signal exceeds the sum of the voltages necessary to cause saturation of any remaining devices in the loop, or when all the devices are being supplied with an input signal. The voltage saturation devices have characteristics as shown in Fig. 1, and may comprise a pair of Zener diodes connected back to back or a double anode Zener diode or a disc of a material such as silicon carbide. As shown in Fig. 2, three voltage saturation devices D A , D B , D C having the same saturation voltages are connected in a ring with a load impedance R L . If any two of the devices are rendered saturated by input currents I the potential across the third is sufficient to make that conductive also and the potential across the load is then equal to the saturation voltage of one of the devices. If all three devices are saturated by input currents then the voltage developed across the load will be three times the saturation voltage of any one device. The circuit may be used as a controlled AND/OR gate. If device D C is not being supplied with an input current then the circuit will only give an output if both the other devices are saturated, if device D C is saturated by an input current, then the circuit will give an output if either of the other two are saturated by an input current. The arrangement may be extended to use more devices, and may make use of devices having a different saturation voltage from the others, normally twice that of the others. In Fig. 3 (not shown) the devices are switched in and out of their saturated condition by connecting the secondaries of three transformers respectively across each, the primaries of each transformer being connected respectively to a PNP transistor. In a binary adder/subtractor, Fig. 5, the inputs are applied in the form of binary pulses to lines A, B, C, the inputs to lines A, B representing the corresponding digits to be added or subtracted and those on lines C any carry pulses. The lines are coupled by way of transformers into a first switching circuit SC1 which produces the carry pulse for the next addition or subtraction and also into a second switching circuit SC2 which produces the sum output on to line OL2. The carry pulse resulting from the addition or subtraction is fed to the output line OL1, and also via a gated inverter IV to circuit SC2 where it is applied to a transformer IA4 connected across a saturation device having twice the saturation voltage of the others in that circuit. The arrangement is such that this device is saturated in the absence of a carry pulse. For subtraction the line A is fed via an inverter into a third switch circuit SC3, the other two lines being coupled directly in by way of further transformer windings, and the switch S is switched to its other condition.