GB938477A - Improvements in or relating to magnetic core memory circuits - Google Patents

Abstract

938,477. Circuits employing bi-stable magnetic elements. ATVIDABERGS INDUSTRIER A.B. July 7, 1960 [July 10, 1959], No. 23794/60. Class 40 (9). A magnetic core memory circuit, Fig. 1, includes a plurality of magnetic cores arranged in sets (cores C11, C12, C1n comprise one set, cores C21, C22, C2n comprise a second set and cores Cn1, Cn2 and Cnn comprise a third set) and each set has a drive winding X1, X2 or X3 connected in series with a normally non-conductive selecting transistor switch Tx1, Tx2 or Txn to constitute a drive path. The drive paths at their one ends are connected together to one pole of a first drive transistor switch Txs and at their other ends are connected together and to one pole of a second drive transistor switch Txr. The drive transistor switches Txs and Txr are normally conductive and have their other poles connected together. An address register ASx is connected to the base electrodes of the selecting transistor switches Tx1, Tx2, Txn and is capable of rendering any of such switches conductive, as desired. A reading pulse genertor LPG and a writing pulse generator SPG are connected to the base electrodes of switches Txr and Txs respectively. The circuit operates on the coincidence principle and further drive paths are provided each consisting of a transistor switch Ty1, Ty2 or Tyn in series with a winding Y1, Y2 or Yn. The further drive paths are connected to drive transistor switches Tyr and Tys and to address register ASy, which operate in a similar manner to switches Txr, Txs and register ASx. Operation.-If core C21 is selected, address registers ASx, ASy render transistors Tx2, Ty1 conductive for a period of time t2 to t7, Fig. 2. At time t3, Fig. 4, a reading pulse from generator LPG is applied to transistor switches Txr, Tyr to block such switches. Current flows from earth, through transistor Txs winding X2 transistor Tx2 and resistor R to a negative source - E2. Current simultaneously flows from earth, through transistor Tys, winding Y1, transistor Ty1 and resistor R to negative source - E2. The sum Ir, Fig. 3, of the ampere-turns at core C21 due to the two currents provides a reading pulse sufficient to reverse the polarity of core C21 and also to induce a voltage pulse in a read-out winding (not shown). After passage of the reading pulse a writing pulse is generated during time t5 to t6 by the application of a pulse from generator SPG to the bases of transistor switches Txs, Tys. The writing pulse resets the core. Surge protection for the transistors is provided by diodes D connected to a source - E1 the voltage of which is higher than the highest possible voltage which may be induced in the windings. Spurious outputs due to capacitive coupling between the read-out winding and unselected windings are prevented by the earth connection over transistors Txs, Tys.