GB938317A - Improvements in or relating to electronic decade counting circuits - Google Patents

Abstract

938,317. Electronic counters. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. March 6, 1962, No. 8493/62. Class 106 (1). A decade counter with a 2-out-of-5 output comprises five toggles, the first four being arranged as a cascade counter logical circuits being so arranged that a second input to the first stage will turn off said stage at the end of the pulse to be counted only when the first, second and fifth stages have been turned on, further gating means reversing the fifth stage only when the first or third stages assumes the " on " condition. In the quiescent condition all stages MA-ME are in the off condition and transistor T12 is conducting. When counting commences earth pulses superimposed on a negative potential are applied from terminal IP through diode gates D1, D2 to both sides of the stage MA. The pulses from IP are also applied to cut-off inverter T11 connected to a 3-AND gate feeding T1. The counter operates as a cascade counter up to a count of 6 except that the fifth stage ME reverses over diodes D9, D10 when MA or MC changes to on whereby two of the leads A-E are marked for each count. The seventh pulse initially registers as 11101 but as the pulse ends the re-operation of inverter T11 adds one to the cascade part of the counter to change the registration to 00011. Similarly, the tenth pulse initially registers as 11011 which is changed by the addition of one and the turning on of the third stage to reverse the fifth stage to 00110. Counting down is effected by bringing the counter first to the quiescent state 00000 and by applying short pulses to those leads A-E which are not marked in the ordinary 2-out-of-5 representation of the digit concerned. Counting down involves an additional 3-gate GM and proceeds in 3-out-of-5 code until a zero state is reached with all five leads A-E marked.