GB933228A - Circuits employing square loop cores - Google Patents

Circuits employing square loop cores

Info

Publication number
GB933228A
GB933228A GB3446059A GB3446059A GB933228A GB 933228 A GB933228 A GB 933228A GB 3446059 A GB3446059 A GB 3446059A GB 3446059 A GB3446059 A GB 3446059A GB 933228 A GB933228 A GB 933228A
Authority
GB
United Kingdom
Prior art keywords
winding
core
terminal
output
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3446059A
Inventor
Frederick Herbert Laishley
Maldwyn Hugh Roberts
Timothy Titley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZF International UK Ltd
Original Assignee
Lucas Industries Ltd
Joseph Lucas Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucas Industries Ltd, Joseph Lucas Industries Ltd filed Critical Lucas Industries Ltd
Priority to GB3446059A priority Critical patent/GB933228A/en
Publication of GB933228A publication Critical patent/GB933228A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/45Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of non-linear magnetic or dielectric devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Containers, Films, And Cooling For Superconductive Devices (AREA)

Abstract

933,228. Circuits employing bi-stable magnetic elements. JOSEPH LUCAS (INDUSTRIES) Ltd. Oct. 11, 1960 [Oct. 12, 1959; July 1, 1960], Nos. 34460/59 and 23044/60. Class 40 (9). In a circuit, Fig. 2, comprising a core C having a substantially square hysteresis loop, switches T1, T2, T4 are connected to input windings L1, L2, L4 respectively, and the arrangement is such that, with a D.C. source connected across capacitor C1, when switch T2 is conductive current flows through winding L2 to magnetize the core in one direction and when switch T1 is conductive current flows through winding L1 to apply a magneto-motive force to the core in the opposite direction, an output appearing in an output winding L3 whenever the remanent state of the core changes. Current flowing through input winding L4 when switch T4 is conductive, applies a magneto-motive force to the core in the same direction as current flow through winding L1. In one arrangement, signals applied to terminal S2 are clock pulses and signals must be applied simultaneously to terminals S1 and S4 (which signals must be out of phase with the signals applied to terminal S2) to produce an output, current flowing through either winding L1, L4 alone being insufficient to change the remanent state of the core. In another arrangement, the circuit is such that signals applied to either terminal S1 or S4 result in an output in winding L3, provided that the remanent state of the core is correctly set. In a further arrangement, Fig. 1 (not shown), the input winding L4 and switch T4 are omitted. Clock pulses are applied to terminal S2 and the circuit produces an output in the form of a train of pulses provided that pulses are applied to terminal S1 out of phase with those applied to terminal S2. The switches may be transistors, cold cathode tubes or other equivalent vacuum or semi-conductor devices. The purpose of capacitor C1 is to minimize the risk of overloading the source of supply when the source supplies power to a plurality of circuits such as those shown. Resistor R2 is so chosen that the capacitor charges slowly when the switches are non- conductive.
GB3446059A 1959-10-12 1959-10-12 Circuits employing square loop cores Expired GB933228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB3446059A GB933228A (en) 1959-10-12 1959-10-12 Circuits employing square loop cores

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3446059A GB933228A (en) 1959-10-12 1959-10-12 Circuits employing square loop cores

Publications (1)

Publication Number Publication Date
GB933228A true GB933228A (en) 1963-08-08

Family

ID=10365921

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3446059A Expired GB933228A (en) 1959-10-12 1959-10-12 Circuits employing square loop cores

Country Status (1)

Country Link
GB (1) GB933228A (en)

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