GB9320511D0 - Multi-level cache system - Google Patents

Multi-level cache system

Info

Publication number
GB9320511D0
GB9320511D0 GB939320511A GB9320511A GB9320511D0 GB 9320511 D0 GB9320511 D0 GB 9320511D0 GB 939320511 A GB939320511 A GB 939320511A GB 9320511 A GB9320511 A GB 9320511A GB 9320511 D0 GB9320511 D0 GB 9320511D0
Authority
GB
United Kingdom
Prior art keywords
level cache
cache system
level
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB939320511A
Other versions
GB2271653A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB9320511D0 publication Critical patent/GB9320511D0/en
Publication of GB2271653A publication Critical patent/GB2271653A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions
GB9320511A 1992-10-13 1993-10-05 Multi-level cache system Withdrawn GB2271653A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US96059892A 1992-10-13 1992-10-13

Publications (2)

Publication Number Publication Date
GB9320511D0 true GB9320511D0 (en) 1993-11-24
GB2271653A GB2271653A (en) 1994-04-20

Family

ID=25503375

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9320511A Withdrawn GB2271653A (en) 1992-10-13 1993-10-05 Multi-level cache system

Country Status (3)

Country Link
JP (1) JPH06202951A (en)
DE (1) DE4323929A1 (en)
GB (1) GB2271653A (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829025A (en) * 1996-12-17 1998-10-27 Intel Corporation Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction
US6275904B1 (en) 1998-03-31 2001-08-14 Intel Corporation Cache pollution avoidance instructions
KR20010016952A (en) * 1999-08-05 2001-03-05 박인규 Impedance-Compensated Power Transmission Circuit
JP2005115603A (en) * 2003-10-07 2005-04-28 Hitachi Ltd Storage device controller and its control method
US7506132B2 (en) 2005-12-22 2009-03-17 International Business Machines Corporation Validity of address ranges used in semi-synchronous memory copy operations
US7454585B2 (en) 2005-12-22 2008-11-18 International Business Machines Corporation Efficient and flexible memory copy operation
US7484062B2 (en) 2005-12-22 2009-01-27 International Business Machines Corporation Cache injection semi-synchronous memory copy operation
JP2009093559A (en) 2007-10-11 2009-04-30 Nec Corp Processor, information processing device and cache control method of processor
US9697002B2 (en) * 2011-10-03 2017-07-04 International Business Machines Corporation Computer instructions for activating and deactivating operands
US9690583B2 (en) 2011-10-03 2017-06-27 International Business Machines Corporation Exploiting an architected list-use operand indication in a computer system operand resource pool
US20130179642A1 (en) * 2012-01-10 2013-07-11 Qualcomm Incorporated Non-Allocating Memory Access with Physical Address

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2261586C3 (en) * 1972-12-15 1979-08-09 Siemens Ag, 1000 Berlin Und 8000 Muenchen Storage facility
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
GB2037038B (en) * 1978-12-11 1983-05-05 Honeywell Inf Systems Cache storage systems
US4500954A (en) * 1981-10-15 1985-02-19 International Business Machines Corporation Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass

Also Published As

Publication number Publication date
DE4323929A1 (en) 1994-04-14
JPH06202951A (en) 1994-07-22
GB2271653A (en) 1994-04-20

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)