GB2264577B - Cache memory system - Google Patents

Cache memory system

Info

Publication number
GB2264577B
GB2264577B GB9303999A GB9303999A GB2264577B GB 2264577 B GB2264577 B GB 2264577B GB 9303999 A GB9303999 A GB 9303999A GB 9303999 A GB9303999 A GB 9303999A GB 2264577 B GB2264577 B GB 2264577B
Authority
GB
United Kingdom
Prior art keywords
cache memory
memory system
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9303999A
Other versions
GB2264577A (en
GB9303999D0 (en
Inventor
Rajendra Kumar
Paul G Emerson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB9303999D0 publication Critical patent/GB9303999D0/en
Publication of GB2264577A publication Critical patent/GB2264577A/en
Application granted granted Critical
Publication of GB2264577B publication Critical patent/GB2264577B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
GB9303999A 1992-02-27 1993-02-26 Cache memory system Expired - Fee Related GB2264577B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84290792A 1992-02-27 1992-02-27

Publications (3)

Publication Number Publication Date
GB9303999D0 GB9303999D0 (en) 1993-04-14
GB2264577A GB2264577A (en) 1993-09-01
GB2264577B true GB2264577B (en) 1995-06-14

Family

ID=25288537

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9303999A Expired - Fee Related GB2264577B (en) 1992-02-27 1993-02-26 Cache memory system

Country Status (3)

Country Link
JP (1) JPH0612323A (en)
DE (1) DE4306077A1 (en)
GB (1) GB2264577B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5603004A (en) * 1994-02-14 1997-02-11 Hewlett-Packard Company Method for decreasing time penalty resulting from a cache miss in a multi-level cache system
KR0146059B1 (en) 1995-04-11 1998-09-15 문정환 Command prefeth method and circuit using the non-referenced prefeth cache
JP3068469B2 (en) 1996-08-28 2000-07-24 新潟日本電気株式会社 Second level cache memory system
US6085292A (en) * 1997-06-05 2000-07-04 Digital Equipment Corporation Apparatus and method for providing non-blocking pipelined cache
US6138208A (en) * 1998-04-13 2000-10-24 International Business Machines Corporation Multiple level cache memory with overlapped L1 and L2 memory access
TW451132B (en) 1998-12-15 2001-08-21 Nippon Electric Co System and method for cache processing
GB2465773A (en) 2008-11-27 2010-06-02 Symbian Software Ltd Data Storage and Access
US20130262767A1 (en) * 2012-03-28 2013-10-03 Futurewei Technologies, Inc. Concurrently Accessed Set Associative Overflow Cache

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2235554A (en) * 1989-08-31 1991-03-06 Sun Microsystems Inc Computer system architecture
GB2248952A (en) * 1990-10-05 1992-04-22 Digital Equipment Corp Hierarchical integrated circuit cache memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2938511B2 (en) * 1990-03-30 1999-08-23 三菱電機株式会社 Semiconductor storage device
EP0457403B1 (en) * 1990-05-18 1998-01-21 Koninklijke Philips Electronics N.V. Multilevel instruction cache and method for using said cache

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2235554A (en) * 1989-08-31 1991-03-06 Sun Microsystems Inc Computer system architecture
GB2248952A (en) * 1990-10-05 1992-04-22 Digital Equipment Corp Hierarchical integrated circuit cache memory

Also Published As

Publication number Publication date
DE4306077A1 (en) 1993-09-02
GB2264577A (en) 1993-09-01
JPH0612323A (en) 1994-01-21
GB9303999D0 (en) 1993-04-14

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19990226