GB921807A - Improvements in or relating to electrical circuits - Google Patents
Improvements in or relating to electrical circuitsInfo
- Publication number
- GB921807A GB921807A GB4390061A GB4390061A GB921807A GB 921807 A GB921807 A GB 921807A GB 4390061 A GB4390061 A GB 4390061A GB 4390061 A GB4390061 A GB 4390061A GB 921807 A GB921807 A GB 921807A
- Authority
- GB
- United Kingdom
- Prior art keywords
- stages
- alarm
- circuit
- gates
- bring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/085—Error detection or correction by redundancy in data representation, e.g. by using checking codes using codes with inherent redundancy, e.g. n-out-of-m codes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
921,807. Counters; testing. STANDARD TELEPHONES & CABLES Ltd. Dec. 7, 1961, No. 43900/61. Class 106 (1). A storage circuit in which a predetermined number of stages are in true condition for the storage of any item of intelligence operates an alarm when it fails to satisfy this condition, and is characterized by means which cause the storage circuit to fail whereby the test circuit is checked. A 2-out-of-5 counter comprises five stages A-E, weighted respectively 0, 1, 2, 4, 7, the digit 0 being represented by operation of D and E. Stepping is performed by applying a TW1 pulse to all stages simultaneously. If 3 or more stages are operative at any one time one of gates G101-G110 passes a strobe pulse to operate bi-stable device Y to bring up an alarm. Alternatively if 4 or more stages are inoperative one of gates G111-G115 operates to bring up the alarm. Connectors C1-C15 are provided. Periodically all the stages of the counter are brought to state 1 and immediately after to state 0 to check the testing circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4390061A GB921807A (en) | 1961-12-07 | 1961-12-07 | Improvements in or relating to electrical circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4390061A GB921807A (en) | 1961-12-07 | 1961-12-07 | Improvements in or relating to electrical circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
GB921807A true GB921807A (en) | 1963-03-27 |
Family
ID=10430847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4390061A Expired GB921807A (en) | 1961-12-07 | 1961-12-07 | Improvements in or relating to electrical circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB921807A (en) |
-
1961
- 1961-12-07 GB GB4390061A patent/GB921807A/en not_active Expired
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