GB9110667D0 - Semiconductor intergrated circuit device - Google Patents
Semiconductor intergrated circuit deviceInfo
- Publication number
- GB9110667D0 GB9110667D0 GB919110667A GB9110667A GB9110667D0 GB 9110667 D0 GB9110667 D0 GB 9110667D0 GB 919110667 A GB919110667 A GB 919110667A GB 9110667 A GB9110667 A GB 9110667A GB 9110667 D0 GB9110667 D0 GB 9110667D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit device
- intergrated circuit
- melted
- semiconductor intergrated
- fuse element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Logic Circuits (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a semi-conductor integrated circuit device having a fuse portion with at least one fuse element (4) which can be melted on the basis of an applied voltage or current. An adjustment portion (10) is also provided for adjusting the operation properties of an internal circuit of the device, the adjustment portion being arranged to supply as output adjusting signals presenting at least two different stages depending on whether the fuse element is melted or not. <IMAGE>
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13226390 | 1990-05-22 | ||
JP26409490 | 1990-10-02 | ||
JP7877891A JP3141417B2 (en) | 1990-05-22 | 1991-04-11 | Semiconductor integrated circuit device and method of manufacturing the same |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9110667D0 true GB9110667D0 (en) | 1991-07-03 |
GB2245099A GB2245099A (en) | 1991-12-18 |
GB2245099B GB2245099B (en) | 1995-01-18 |
Family
ID=27302802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9110667A Expired - Fee Related GB2245099B (en) | 1990-05-22 | 1991-05-16 | Semi-conductor intergrated circuit device |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP3141417B2 (en) |
KR (1) | KR910020880A (en) |
GB (1) | GB2245099B (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0563852A1 (en) * | 1992-04-02 | 1993-10-06 | Siemens Aktiengesellschaft | Zag fuse for reduced blow-current applications |
TW247368B (en) * | 1993-09-29 | 1995-05-11 | Seiko Epuson Co | Current regulating semiconductor integrate circuit device and fabrication method of the same |
JP2003036673A (en) | 2001-07-24 | 2003-02-07 | Mitsubishi Electric Corp | Semiconductor memory |
JP2005039220A (en) * | 2003-06-26 | 2005-02-10 | Nec Electronics Corp | Semiconductor device |
DE102004014925B4 (en) | 2004-03-26 | 2016-12-29 | Infineon Technologies Ag | Electronic circuit arrangement |
JP4854713B2 (en) * | 2008-07-22 | 2012-01-18 | 株式会社リコー | Manufacturing method of semiconductor integrated circuit having voltage setting circuit |
JP2012033972A (en) * | 2011-11-04 | 2012-02-16 | Renesas Electronics Corp | Semiconductor device |
-
1991
- 1991-04-11 JP JP7877891A patent/JP3141417B2/en not_active Expired - Fee Related
- 1991-05-16 GB GB9110667A patent/GB2245099B/en not_active Expired - Fee Related
- 1991-05-22 KR KR1019910008209A patent/KR910020880A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR910020880A (en) | 1991-12-20 |
GB2245099B (en) | 1995-01-18 |
GB2245099A (en) | 1991-12-18 |
JP3141417B2 (en) | 2001-03-05 |
JPH04218935A (en) | 1992-08-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100516 |