GB2245099A

GB2245099A - Semi-conductor integrated circuit with fuses

Info

Publication number: GB2245099A
Application number: GB9110667A
Authority: GB
Inventors: Kanji Aoki
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 1990-05-22
Filing date: 1991-05-16
Publication date: 1991-12-18
Anticipated expiration: 2011-05-16
Also published as: KR910020880A; GB2245099B; JP3141417B2; JPH04218935A; GB9110667D0

Abstract

The invention provides a semi-conductor integrated circuit device having a fuse portion with at least one fuse element (4) which can be melted on the basis of an applied voltage or current. An adjustment portion (10) is also provided for adjusting the operation properties of an internal circuit of the device, the adjustment portion being arranged to supply as output adjusting signals presenting at least two different stages depending on whether the fuse element is melted or not. <IMAGE>

Description

SEMI-CONDUCTOR INTEGRATED CIRCUIT DEVICE The present invention relates to a semi-conductor integrated circuit device having fuse elements which can be melted by an external voltage or current applied after the assembly of the device as a package.

A semi-conductor integrated circuit is known, in which the composition of an internal circuit and an operation potential and so on can be modified by applying a voltage to an external terminal after the circuit has been assembled by sealing a semi-conductor chip with resin. For example, an EPROM (erasable and programmable read only memory) is known with built in FAMOSts using a floating gate. EPROMs have the advantage that they can be freely written and erased. However, they also have the disadvantage that the manufacturing process for forming the FAMOS is complicated and hence the manufacturing cost is high.

On the other hand, a semi-conductor integrated circuit, which can be manufactured at a low price, is also kIsown in the form of a PROM (programmable read only memory), in which data can be written by melting a fuse.

Another known semi-conductor integrated circuit has multiple sets of fuses (fuse bits) for setting a logical state in an input portion of an internal circuit, the fuses being selectively melted before the device is sealed with resin in order to adjust an oscillation frequency of a built in crystal oscillator in the integrated circuit and an output voltage of a regulator.

Figure 8 shows the structure of one section of a semi-conductor integrated circuit device having a set of these fuse bits. In this Figure, a first terminal 1 is set at ground potential, a second terminal 2 is connected to a power source supplying a voltage of 5 V.

An input terminal 3 is connected to a junction between a fuse element 4 and a load MOS 5. The resistance value of the load MOS 5 is several tens of k ohms, and that of the fuse element 4 is several tens of ohms. The electric potential at the input terminal 3 is supplied to an internal circuit 11 through a resistance R. In a device having such a structure, although it is impossible to restore the fuses to their initial connected state once they are melted, there is the advantage that the device can be produced at a low price.

The fuse itself may comprise a polysilicon layer having an appropriate sheet resistance value, in which case the fuse is melted by supplying an excess current, or it may comprise thin insulating film between polysilicon or metal layers, in which case the fuse is rendered conductive with a prescribed resistance value by destroying the insulating film by applying a high electric field.

Thus, in a semi-conductor integrated circuit with built in fuses, the desired internal circuit structure and so on is formed by partially severing the fuse elements prior to the assembly of the IC package within resin and the like. A semi-conductor chip whose internal circuit is formed in this way is shown in Figure 7, which illustrates the package structure of a real time clock having a crystal oscillator 16. After wires 17a, 17b are bonded to the semi-conductor chip 15 and to external terminals 18a, 18b, the chip 15 together with the external terminals 18a, 18b is sealed with resin.In moulding the semi-conductor chip within the resin, however, stress due to pressure and temperature is exerted on the semi-conductor chip 15 and the crystal oscillator 16 and so on, and hence the resistance division ratio inside the internal circuit, the threshold voltage of any active element or the oscillation frequency of the crystal oscillator and so on change. As a result, the characteristics of the semi-conductor integrated circuit may deviate from an optimum value. There is also the problem that the characteristics of a plurality of the manufactured devices may vary widely.

A polysilicon fuse which normally is melted prior to the assembly of a package is difficult to melt completely after the assembly of the package, even if a high voltage is applied, on account of the mould material with which the semi-conductor chip is sealed.

For example, it often happens that only a central part of the polysilicon layer is disrupted by the heating of the melting currrent so that unsevered parts remain on both sides. Once this happens, the resistance value of the fuse becomes extremely high and it becomes very difficult thereafter to apply a melting current sufficient to melt the fuse completely.

Furthermore, in the case of a semi-conductor integrated circuit in which one or more fuses are utilised in the input portion to adjust the internal circuit, even if the fuse element is fully severed on the basis of the data of the internal circuit provided beforehand, there is the possibility that the characteristics of different semi-conductor devices will vary on account of variations in each circuit constant arising in the manufacturing process. Accordingly, even if each device is adjusted equally, it is not always possible to set an oscillation frequency and output voltage of the internal circuit at the optimum value.

It is an object of the present invention to provide a semi-conductor integrated circuit whose internal circuit can be adjusted regardless of changes in the characteristics arising in the packaging process.

Although the present invention is primarily directed to any novel integer or step, or combination of integers or steps, herein disclosed and/or as shown in the accompanying drawings, nevertheless, according to one particular aspect of the present invention to which, however, the invention is in no way restricted, there is provided a semi-conductor integrated circuit device having a fuse portion with at least one fuse element which can be melted on the basis of an applied voltage or current, and an adjustment portion for adjusting the operation properties of an internal circuit of the device, the adjustment portion being arranged to supply as output adjusting signals presenting at least two different states depending on whether said at least one fuse element is melted or not.

It is desirable that the fuse element be formed from wiring material such as aluminium, or an aluminium alloy containing Si, Cu, Ni, Co, Ti and so on. In this case, it is to be desired that the resistance value of the fuse element be higher than 10 ohms. By forming the fuse element of the device from an appropriate material, a sufficient degree of melting can be ensured after the assembly of a package including the device.

Preferably, a part of the fuse element to be melted has a reduced section in a direction which is perpendicular to that of the supply of voltage or current. For example, if the fuse element is in the form of a strip, the part to be melted may be of reduced width and/or thickness.

It is also preferable to form the fuse element on the margin of the internal circuit and to form the part to be melted near the edge of the fuse element.

In the manufacturing process, the fuse element may be formed simultaneously with one of the wiring layers of the device, preferably the lowest, and from the same material. The fuse element may also be formed on a stepped portion of the device.

By combining the fuse portion and the adjusting portion, the device can always be adjusted appropriately depending on whether the fuse element is melted or not, regardless of variation in the properties of the internal circuit and so on.

Preferably, the adjustment portion comprises test signal input means, and signal selecting means for selecting either the adjusting signals or test signals introduced from the test signal input means and for supplying the selected signals to the internal circuit.

The invention is particularly applicable to a semi-conductor integrated circuit device having an internal circuit comprising a timing circuit equipped with a standard oscillation source, at least one dividing circuit for dividing signals supplied by the standard oscillation source, and a control portion for supplying the adjusting signals to the dividing circuit at prescribed intervals.

The present invention will be described further, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a plan view showing the composition of a fuse element of an input portion of a semi-conductor integrated circuit according to the present invention; Figure 2 is a graph showing the relation between resistance value and an electro-static discharge withstanding capability rating for the fuse element shown in Figure 1; Figure 3 is a circuit diagram of a series regulator whose output voltage can be adjusted by fuse elements as shown in Figure 1; Figure 4 is a circuit diagram of an input portion of a second embodiment of a semi-conductor integrated circuit according to the present invention; Figure 5 is a circuit diagram showing an application of the input portion shown in Figure 4 in an oscillation circuit;; Figure 6 is a circuit diagram of a logical circuit of the oscillation circuit of Figure 5 for adjusting a pulse rate for a real time clock; Figure 7 is a cross section showing the composition of a semi-conductor integrated circuit package including a crystal oscillator; and Figure 8 is a circuit diagram of a fuse portion of a conventional semi-conductor integrated circuit.

Figure 1 shows a ground plan of the pattern or arrangement of a fuse portion of a semi-conductor integrated circuit according to the present invention.

This fuse portion is formed from two aluminium layers, which are formed one above the other in the same process in which aluminium wiring of an internal circuit is formed. The upper aluminium layer provides an input pad 20 about 120 pm square having a pad opening 20a on its surface. A connection 20b formed integrally with the input pad 20 is electrically connected through a contact hole 21 to one end 22a of a fuse strip 22 provided by the lower aluminium layer. The other end 22b of the fuse strip 22 is electrically connected to a source line 24, which is at ground potential, through a contact hole 23. Note that the right part of the source line 24 is a formation domain of the internal circuit.

Another convection 20c, which is also formed integrally with the input pad 20, is connected through a contact hole 25 to a polysilicon resistance layer 26 and thence to an electro-static protective signal line 28 by way of a contact hole 27. The signal line 28 is connected to the internal circuit through an electro-static protective diode.

The fuse strip 22 has a thickness of about 5000 A, the material thereof being an aluminium alloy made by doping aluminium used as a wiring material with 1% silicon, and it has a sheet resistance of about 60 m ohms. Normally, the lower layer is thinly formed for providing the aluminium wiring, and therefore is also appropriate for the fuse strip 22 for providing a required resistance value in an area as small as possible. The lower layer in this instance may constitute the lowest of a number of wiring layers. The resistance value of the fuse strip 22 is 15 ohms, the width is about 5 pm, and the length is about 1.2 mm.

In a left hand portion of the fuse strip 22 as shown, a 3 pm wide narrow part 22s is formed. The width of the narrow part 22s is preferably selected so as to match the minimum size available in the manufacturing process for a semi-conductor integrated circuit, in which the case the widths of the other sections of the fuse strip 22 can be narrowed correspondingly. As a result, the area occupied by the fuse strip 22 can be minimised.

The narrow part 22s defines the portion separated by melting and, since the width is narrowed here, incomplete melting is avoided and stable melting properties are achieved. Furthermore, since the narrow part 22s is remote from the internal circuit, the internal circuit is hardly affected by the heat during the melting even if a protective film in the vicinity is damaged. Note that the narrow part 22s is not limited to the formation employed in the present example. It is possible to establish several narrow parts, and to ensure that one of them is melted. It is also possible to employ a thin part, whose layer thickness is reduced, instead of a narrow part 22s. Of course, it is possible to reduce both the width and the thickness of this part of the fuse strip 22.

In particular, if the fuse strip 22 is formed by normal sputtering or metallising techniques on a stepped portion of an integrated circuit necessarily produced in the manufacturing process, for example a stepped portion formed between the formation domain and nonformation domain of a selective oxide film, or a stepped portion formed on the surface of an inter-layer insulating film spanning the area between the lower formation domain and the non-formation domain of wiring, a thin part is naturally formed at the stepped portion.

Hence, it is not necessary to modify either the shape of a mask pattern or an accumulation process.

The shape of the fuse strip 22 is determined according to the following requirements: (i) The fuse strip 22 must melt stably when an external voltage is applied.

(ii) The fuse strip 22 must not melt when it touches input and output pins, that is to say it must not melt when the source voltage (5 V in this example) is applied to the input pad 20.

(iii) The fuse strip 22 must withstand an electric current from the input pad caused by static electricity.

That is to say, as a standard, it must withstand a test discharge from a capacitance of 200 pF charged with 200 V (200 V, 200 pF, 0 ohms).

(iv) The fuse strip 22 must maintain insulation properties after it has melted. In other words, it must sufficiently withstand a high temperature and high humidity environment.

The melting voltage must be higher than 7 V, considering requirement (ii) above and a suitable margin for a 5 V source voltage. Meanwhile, the melting current of the fuse strip 22 is required to be less than 1 A, because it must be less than the melting current for bonding wires connected to the input pad 20 in the semi-conductor integrated circuit. Under such conditions with regard to voltage and electric current, the resistance value must be adjusted to meet requirement (iii) above. Figure 2 represents graphically a rating for the ability of the fuse strip 22 to withstand an electro-static discharge obtained in pressure testing for a capacitance of 200 pF, 0 ohms, when the width and thickness of the fuse strip 22 is set invariably and the resistance value is changed simply by changing the length of the fuse strip 22. According to Figure 2, a fuse strip having a resistance value of 8 ohms is melted at 200 V, and a fuse strip having a resistance value of 10 ohms is melted at 250 V. Therefore, the resistance value of the fuse strip must be higher than 10 ohms.

Note that, if the fuse strip 22 has a narrow part 22s as described above, the value of the melting current is reduced, and also its electro-static discharge withstand rating lowers, compared with the case in which the fuse strip 22 does not have a narrow part 22s. Accordingly, it is then necessary to raise the resistance value further in view of the decrease in the electro-static discharge withstand rating. On the other hand, if the width of the fuse strip 22 is increased whilst maintaining the resistance value, although the electro-static discharge withstand rating increases, the melting current also increases, and the limitation of requirement (ii) applies. Moreover, the area occupied by the fuse strip must be extended to obtain the desired degree of resistance.

In view of the above considerations and the requirements (i) and (iv), the dimensions of the fuse strip 22 are determined. The melting voltage of the fuse strip 22 is 20 V, and the melting current is 600 mA. In the present example, by using aluminium silicon having a low resistance as the material of the fuse strip 22, conventional bad melting can be prevented.

Furthermore, even if bad melting occurs and a residual bridge remains, the resistance value is not much raised as a result of the residual bridge. Therefore, the fuse can be melted with a high degree of certainty and stability.

Consequently, when the internal circuit is a real time clock with a crystal oscillator and a regulator for example, it is possible to adjust the oscillation frequency and output voltage with certainty and, hence, to improve the yield of the semi-conductor integrated circuit significantly. And since the aluminium silicon used in this example is employed as a wiring material to prevent diffusion of silicon, the fuse strip can be formed simultaneously with the wiring without a special process. Accordingly, a semi-conductor integrated circuit can be manufactured at a low price.

Figure 3 is a circuit diagram of a series regulator having fuse portions 30, 31 whose structure is the same as that shown in Figure 1. An input voltage applied to an input terminal 35 generates a prescribeS output voltage between output terminals 36 and 37.

Analog switches 33a, 33b and 33c, 33d, which constitute a switch block 33, are respectively connected between four division points of a resistance R and the non 0 inverting input of a comparator 34. Two bit data, set according. to whether the fuse strip in each of the fuse portions 30, 31 is melted or not, is introduced to the switch block 33 through a decoder 32 and serves to close a corresponding analog switch in the switch block 33.

In this way, it is possible to change the potential tap point in the resistance R for selectively controlling 0 the voltage introduced to the non-inverting input of the comparator 34 depending on whether the fuse strip of each of the input portions 30, 31 is melted or not. It thus becomes possible to adjust the output voltage correspondingly.

Next, a second embodiment of the present invention will be explained. In this embodiment, an input portion of a semi-conductor integrated circuit having a fuse element 4 has a circuit as shown in Figure 4. As shown in Figure 4, the fuse element 4 is connected between a first power source line 1 and an input terminal 3, and a p-channel field effect transistor 5 is connected between the input terminal 3 and a second power source line 2. The fuse element 4 normally has a resistance value 10 ohms to 20 ohms, and the field effect transistor 5 has a suitable resistance value in relation to the resistance value of the fuse element 4.

A latch register 9 serves to latch test signals TS on the basis of clock signals CLK, the output from the latch register 9 and an input from said input terminal 3 being supplied to a select circuit 10. The select circuit 10 is composed of an AND gate and an OR gate.

When selector controlling signals SC input to the select circuit 10 are at a logically high level, input signals from the input terminal 3 are selected and are sent to an internal circuit 11. On the other hand, when the selector controlling signals SC are at a logically low level, the data of the latch register 9 is selected and is output to the internal circuit 11 to determine an adjusting input for the internal circuit 11.

The fuse element 4 is preferably a polysilicon layer, but an aluminium silicon layer can also be used as in Figure 1. The fuse element 4 may be of a kind which disconnects an electric conductor or resistance, or it may be of a kind which generates a short circuit by destroying a pn-junction, or which constitutes an insulating film formed between layers of an electric conductor and which produces a short circuit by the breakdown of the insulating film, and so on.

The latch register 9 can be a latch circuit such as a D flip flop, a JK flip flop, and an RS flip flop.

As the internal circuit, a circuit for detecting a fall in source voltage and a regulator circuit can be used. The output of the select circuit 10 is then used to set a resistance division ratio to one of a plurality of selection values corresponding to a bit number of the fuse element in order to adjust the detected voltage and the regulation voltage. Of course, the select circuit 10 may be used to control the frequency of clock signals in an integrated circuit with a built in clock.

This example operates as follows: to adjust said internal circuit, test signals TS are introduced to the latch register 9 in advance with the selector controlling signals SC set at a logically high level.

Then, after confirming the operation of the internal circuit on the basis of the test signals, the input potential can be adjusted by selecting whether or not to melt the fuse element 4. Consequently, adjustment errors caused by variations in the internal circuit can be minimised.

In one application of the second embodiment shown in Figure 5, the input portion is employed to adjust the oscillation frequency of an oscillation circuit having a crystal oscillator. In this example, a shift register 12 comprising five D flip flops receives test signals TS as input and supplies five output signals QO, Q1, Q2, Q3, Q4 in parallel from the outputs of the respective D flip flops on the basis of the clock signals CLK. These output signals QO, Q1, Q2, Q3, Q4 are introduced to respective select circuits SO, S1, S2, S3, S4 together with inputs from five fuse bits F0, F1, F2, F3, F4 (each composed of an input terminal 3, a fuse element 4 and a field effect transistor 5 as shown in Figure 4). Common select controlling signals SC are introduced to the select circuits SO, S1, S2, S3, S4, and, depending on the signal level of the select controlling signals SC, either the output signals QO, Q1, Q2, Q3, Q4 or the inputs from the fuse bits F0, F1, F2, F3, F4 are selected in the same way as stated above and are introduced to bit inputs CO, C1, C2, C3, C4 of a logical circuit 13 for adjusting a pulse rate which controls a dividing stage of an oscillation circuit.

The logical circuit 13 adjusts the pulse rate by changing the division ratio of the dividing stages on the basis of the bit inputs. For example, it can lead compensate or delay compensate an oscillation frequency of 32.768 kHz in steps of five bits.

Figure 6 is a circuit diagram of the logical circuit 13 for adjusting the pulse rate. In this circuit, in response to standard signals generated by a crystal oscillator OSC, clock signals are output on an output terminal OUT at intervals of one second through a lead compensating circuit A composed of four 1/2 dividing stages Al to A4, a delay compensating circuit B composed of one 1/2 dividing stage, and a dividing circuit C. A circuit D generates control signals d at a rate of one controlling pulse per interval of ten seconds, for instance, on the basis of the clock signals. The controlling signals d are supplied to a control input selection block E having a respective switching part corresponding to each of the dividing stages.

When a controlling pulse is input, bit inputs CO, C1, C2, C3, C4 are introduced from the input portion shown in Figure 5 to set inputs S of each of the 1/2 dividing stages Al to A4, and a re-set input R of the 1/2 dividing stage of the delay compensating circuit B.

If a bit input "0" is introduced to the set input S of any of the 1/2 dividing stages Al to A4, the respective dividing stage Al to A4 continues generating a divided output. On the other hand, if a bit input "1" is introduced, the output of the respective dividing stage Al to A4 becomes "1" at that point, and lead compensation is carried out for the input signal to the respective dividing stage Al to A4. If a bit input "0" is introduced to the re-set input R of the 1/2 dividing stage of the delay compensating circuit B, output signals of the lead compensating circuit A are 1/2 divided and are output. If a bit input "1" is introduced, the output of the delay compensating circuit B becomes "0" at that point, and delay compensation is carried out for the input signal of the delay compen sating circuit B.

In this way, the timing of clock signals in a logical circuit for adjusting a pulse rate can be lead compensated or delay compensated at prescribed intervals according to the respective states of bit inputs C0, C1, C2, C3, C4, as shown in Table 1. In a real time clock, the oscillation frequency of a crystal oscillator is 32.768 kHz, and when the controlling signal d output by the circuit D includes a controlling pulse in each interval of ten seconds, the lead compensation or delay compensation can be carried out for 3ppm clock signals for each step of the bit input.

TABLE 1 Pely

-16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 C1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 t4 ~OI 0 0 0 C5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cs JJ.

Lead

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 In this application, serial data in the test signals TS is converted to a corresponding bit number through the shift register 12, and is introduced to the respective bit inputs CO, C1, C2, C3, C4 of the logical circuit 13 for adjusting the pulse rate. Then, the dependency of the oscillation circuit on frequency is measured. Consequently, the properties of the oscillation circuit, that is to say, the correlation between the logical state of the logical circuit 13 for adjusting the pulse rate and the oscillation frequency can be established in a very short time.By selecting whether or not to melt the fuse bits FO, F1, F2, F3, F4 on the basis of this measurement data, the frequency can be adjusted extremely precisely even in the case of oscillation circuits whose frequency dependency varies widely.

The present invention as described is characterised by an input portion with built in fuse elements in a semi-conductor integrated circuit for internal adjustment of the operation properties of an internal circuit. Aluminium or an aluminium alloy, which is employed as the wiring material, is used as the fuse element. The input portion includes means for the input of test signals and means for the selection of signals.

Accordingly, the properties of the internal circuit can be adjusted by applying a voltage or an electric current from an external source after the assembly of the semi-conductor integrated circuit package. Therefore, the internal circuit can be adjusted optimally without its properties subsequently being affected by stress due to applied pressure and temperature and so on in the manufacturing process, and particularly in the resin sealing stage of the manufacturing process.

When the fuse element is formed from the aluminium or aluminium alloy wiring material, it can be melted stably. Even if a bridge like part remains due to incomplete melting, further melting is easy since the resistance rate is much lower than that of a conventional polysilicon layer. Moreover, since the fuse element is formed from the wiring material, it can be formed simultaneously with the wiring.

By setting the resistance value of the fuse element having a low resistance rate at higher than 10 ohms, the electric discharge withstand capability rating can be sufficient for the general external environment.

By forming at least one portion of the fuse element as a section of reduced area, the melting stability of the fuse element can be improved. Also, by forming the part to be melted near a portion of the fuse element which is at the margin of the semi-conductor integrated circuit, the danger of destruction of a covering film and of affecting the internal circuit and so on when melting the fuse can be minimised.

If the fuse element is formed simultaneously with other wiring layers, the number of steps in the manufacturing process need not be increased and so an increase in manufacturing cost can be avoided. The lowest wiring layer of an integrated circuit is normally thin. Therefore, if the fuse element is formed simultaneously with the lowest wiring layer, a very thin fuse layer can be obtained without reducing a plane pattern or altering the formation time. Consequently, the necessary resistance value may be obtained with the shortest possible fuse element, and the area occupied by the fuse element may be minimised.In setting up the part of the fuse element to be melted, it is advantageous to form the fuse element on a stepped portion formed by LOCOS (selective oxide film) or on an interlayer insulating film and so on formed over a difference in level at the border of a polysilicon layer or an aluminium wiring layer, so that a stepped portion is also formed in the fuse element. This stepped portion is made to be thinner than the other plane parts of the fuse element, and, consequently, a portion to be melted can be formed without changing the pattern shape of the fuse element, the formation time, and so on.

By controlling signal selection means on the basis of selection controlling signals, and by operating the internal circuit after introducing test signals, it is possible to detect the operation data of an internal circuit and to melt one or more fuse elements on the basis of this data. Accordingly, the properties of the internal circuit can be adjusted stably and highly precisely.

In the case of a semi-conductor integrated circuit having multiple fuses and means to select signals, a shift register can be used as means to input the test signals. In this case, after serial signals are input, a parallel output can be obtained by the shift register.

Accordingly, by simply inputting one serial signal as a test signal, the entire adjusting data corresponding to multiple adjusting signals can be obtained in a short time.

Claims

1. A semi-conductor integrated circuit device having a fuse portion with at least one fuse element which can be melted on the basis of an applied voltage or current, and an adjustment portion for adjusting the operation properties of an internal circuit of the device, the adjustment portion being arranged to supply as output adjusting signals presenting at least two different states depending on whether said at least one fuse element is melted or not.

2. A device as claimed in claim 1 in which said at least one fuse element is formed from aluminium or aluminium alloy providing a wiring material for the device.

3. A device as claimed in claim 1 or 2 in which the resistance value of said at least one fuse element is equal to or higher than 10 ohms.

4. A device as claimed in claim 1, 2 or 3 in which said at least one fuse element has a part to be melted, whose section in a direction perpendicular to the direction of the supply of voltage or current is reduced.

5. A device as claimed in claim 4 in which said at least one fuse element is in the form of a strip and said part to be melted has a narrowed width.

6. A device as claimed in claim 4 in which said at least one fuse element is in the form of a strip and said part to be melted has a reduced thickness.

7. A device as claimed in claim 4, 5 or 6 in which said at least one fuse element is formed on the margin of the internal circuit, and said part to be melted is formed near the edge of said at least one fuse element.

8. A device as claimed in any preceding claim in which the adjustment portion comprises a resistance and a switch block having a plurality of switches, which are respectively connected to corresponding tap points of the resistance and which are arranged to be opened and closed depending on the state of said at least one fuse element.

9. A device as claimed in any of claims 1 to 7 in which the adjustment portion comprises test signal input means, and signal selecting means for selecting either the adjusting signals or test signals supplied from the test signal input means.

10. A device as claimed in claim 9 in which the adjustment portion comprises a plurality of the fuse elements and a plurality of signal selecting means associated with the fuse elements, the test signal input means comprising a shift register arranged to supply parallel outputs to the signal selecting means as the test signals.

11. A device as claimed in any preceding claim in which the internal circuit comprises a timing circuit having a standard oscillation source, at least one dividing circuit for dividing signals output by the standard oscillation source, and a control portion for receiving the adjusting signals and supplying the adjusting signals to the dividing circuit at prescribed intervals.

12. A device as claimed in any preceding claim which is sealed with resin.

13. A method of manufacturing a semi-conductor integrated circuit device as claimed in claim 1, in which said at least one fuse element is formed simultaneously with a wiring layer of the device and from the same material.

14. A method as claimed in claim 13 in which the wiring layer is formed as the lowest wiring layer of the device.

15. A method as claimed in claim 13 or 14 in which said at least one fuse element is formed on a stepped portion of the device.

16. A semi-conductor integrated circuit device substantially as herein particularly described with reference to and as illustrated in the accompanying drawings.

17. A method of manufacturing a semi-conductor integrated circuit device substantially as herein particularly described with reference to and as illustrated in the accompanying drawings.

18. A semi-conductor integrated circuit device having at least one fuse element which can be melted on the basis of the application of voltage or an electric current on an external terminal, an internal adjustment input part which outputs adjusting signals presenting at least two different states depending on whether said fuse element is melted or not, and an internal circuit whose operation properties can be adjusted on the basis of said adjusting signals.

18. A semi-conductor integrated circuit device having an input terminal which is electrically connected to a first source potential through high resistance, at least one fuse element which is electrically connected between said input terminal and a source potential and which can be melted on the basis of the application of voltage or an electric current, an internal adjustment input part which outputs adjusting signals presenting at least two different states depending on whether said fuse element is melted or not, and an internal circuit whose operation properties can be adjusted on the basis of said adjusting signals, wherein said internal adjustment input part has a test signal input-means, and a signal selecting means for selecting either said adjusting signals or test signals introduced from said test signal input means and for introducing the selected signals to said internal circuit.

19. A method of manufacturing a semi-conductor integrated circuit device having at least one fuse element which can be melted on the basis of the application of voltage or an electric current on an external terminal, an internal adjustment input part which outputs adjusting signals presenting at least two different states depending on whether said fuse element is melted or not, and an internal circuit whose operation properties can be adjusted on the basis of said adjusting signals, wherein said fuse element is formed simultaneously with a wiring layer from the same material as that of a wiring layer made from aluminium or aluminium alloy.

20. Any novel integer or step, or combination of integers or steps, hereinbefore described and/or as shown in the accompanying drawings, irrespective of whether the present claim is within the scope of or relates to the same, or a different, invention from that of the preceding claims.