897,167. Controlled non-linear inductors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 20, 1960 [Sept. 28, 1959], No. 32267/60. Class 40 (9). [Also in Group XIX] A bi-stable circuit, Fig. 1, comprises two saturable cores 10, 11 with remanent properties having input windings 12, 13 associated with a plurality of input terminals 31, 32, 33, 34, and output windings 14, 15 connected between an A.C. source terminal 16 and an output terminal 18, the input windings being shunted by a diode 17 arranged to be non-conductive to positive inputs and to a positive feed-back signal applied from the output circuit to input terminal 34, and the windings being arranged in the same sense on core 10 and opposing sense on core 11. Operation of basic device. In the absence of a positive input pulse, the magnetic state of both cores, alternates between the two saturation levels, and the consequential high impedance of windings 14, 15 prevents an effective output. As the input windings 12, 13 are connected in series opposition no secondary output is produced by transformer action. When a positive pulse is applied to the input windings the core flux conditions are unbalanced so that saturation is achieved at different times. As soon as one core saturates, the other core is able to produce an effective induced secondary output which passes through a short-ciruit path provided by the shunting diode 17. In consequence the series impedance of both output windings is low and an effective output is obtained at terminal 18. This output is maintained by the positive feed-back after the input pulse terminates. The circuit is restored to its original state of negligible output by a negative input pulse which over-rides the positive feedback. Output circuit. A positive output is obtained at terminal 29 from a branch circuit comprising rectifier 27, capacitor 24 and resistors 25 and 26, and the positive feed-back voltage is derived from an intermediate terminal 30. A negative output at terminal 28 is produced by a branch circuit comprising rectifier 23 and resistor 21. The conductive condition of the bi-stable circuit is also indicated by a lamp 19. Logical operations. The relative polarities of coincident input pulses on terminals 31, 32 and 33 enable various logical operations to be effected. Examples are positive pulses on all terminals for the logical operation OR, positive pulses X, Y on two terminals and a negative pulse Z on one terminal for the logical function (X+Y)Z, and a positive pulse on one terminal and the other inputs negative for the logical function X(Y+Z). Duodecimal counter. Each counting stage, Fig. 3, is of the kind shown in Fig. 1 and is represented by a square having an A.C. terminal 16, negative and positive output terminals 28, 29 and input terminals 31, 32, 33. Each count of three pulses in the upper series of stages 0, 1, 2 causes a one-stage shift along the lower series of stages 0, 3, 6, 9. Initially only the two 0 stages are arranged to produce effective outputs. The pulses to be counted are positive and are applied to terminals 31 of all the stages in the upper series. The first stage of each series applies an inhibiting negative potential to terminals 32 of all the succeeding stages except the one (stage 1 and stage 3) immediately following. The first counting pulse brings stage 1 into the conductive state, and the negative output from this stage brings stage 0 in the first series into the non-conducting state when the counting pulse terminates. The next counting pulse transfers the count to stage 2 and so on. The third pulse in combination with a positive output at terminal 29 of stage 2 opens an AND gate 40 and causes the conductive state in the lower series to be transferred from stage 0 to stage 3. The twelfth pulse also passes through AND gate 40 and combines with the output of stage 9 to produce a count of twelve output from AND gate 41. Decimal counter. The circuit shown in Fig. 5 makes use of the property that two adjacent stages are conducting for the duration of a counting pulse. In the upper series the third pulse brings both stages 2 and 0 into conduction and their positive outputs open AND gate 40. This brings stage 3 into the conductive state. In a similar manner each count of three pulses causes a one-step progression along the lower series of stages. After the ninth pulse stage 9 is conducting. The tenth pulse causes stage 0 in the lower series to conduct, this stage having a direct connection from terminal 31 to the pulse source and being inhibited when either stages 3 or 6 is conducting. As stage 9 remains conducting the two positive outputs open an output AND gate 41. Counting in the upper series is prevented by an inhibiting connection from the negative output of stage 9 to stage 1, and at the completion of the tenth pulse only stages 0 in both series are conductive in preparation for a new counting cycle. An alternative circuit is shown in Fig. 4 in which stage 0 in the lower series becomes conductive at the tenth pulse due to the output from stage 9 opening an AND gate 42. Counter modified for operation either as decimal or duodecimal. The Fig. 4 circuit is modified by the provision of switches between the input terminal 32 of stage 1 and the negative output terminal of stage 9, and between the input terminal 31 of stage 0 of the lower series to connect either the source of input pulses or the output of AND gate 40. With the first switch open and the second switch providing a connection to gate 40, the Fig. 4 circuit is converted to the equivalent of Fig. 3 and permits counting to the base of 12. Visible display system. The lamps 19 of the two lines are co-ordinately arranged as shown in Fig. 6 in association with light ducts. Thus when lamp 19 1 of the upper series and lamp 19 3 of the lower series are both illuminated, corresponding to the count of four, the digit 4 in the display has maximum illumination. The use of ducts may be avoided by fitting each lamp with a rectilinear filament able to illuminate a complete column or row.