GB886422A - Improvements in or relating to data processing apparatus - Google Patents
Improvements in or relating to data processing apparatusInfo
- Publication number
- GB886422A GB886422A GB26168/61A GB2616861A GB886422A GB 886422 A GB886422 A GB 886422A GB 26168/61 A GB26168/61 A GB 26168/61A GB 2616861 A GB2616861 A GB 2616861A GB 886422 A GB886422 A GB 886422A
- Authority
- GB
- United Kingdom
- Prior art keywords
- adder
- digit
- carry
- circuit
- added
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
- G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Testing Of Balance (AREA)
- Control Of Positive-Displacement Pumps (AREA)
- Control Of Turbines (AREA)
Abstract
886,422. Correcting binary-coded arithmetic operations. MINNEAPOLIS-HONEYWELL REGULATOR CO. Jan. 24, 1958 [Jan. 25, 1957], No. 26168/61. Divided out of 886,421. Class 106 (1). In an accumulator/adder in which binarycoded (1-2-4-8) decimal digits are added or subtracted in series by bit, in series by digit, a filler digit is always added to one of the digits by 6-adder 480 before it is entered in the main adder 481 if the operation is addition, and, if there is no carry from the operation in adder 481, a further digit is added to the sum output by 10-adder 485 to counteract the effect of the filler digit. Inputs from circuits 490 and 494 or 495 are applied both to the main adder 481 and a carry determining circuit 482. If a carry occurs the ten generator 487 is inhibited and the output of adder 481 passes unchanged through 10-adder 485 from where it may be recirculated to circuits 490, 491, 494 or 495. On subtraction the 6-adder 480 is inhibited and the digit from input circuits 490 or 491 is complemented. A 1 is always added to the main adder from circuit 482 and if there is no carry in circuit 482 the ten generator operates the 10-adder 485. The answer may be complemented by passing it through circuit 492 on a second pass through the accumulator.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US886422XA | 1957-01-25 | 1957-01-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB886422A true GB886422A (en) | 1962-01-03 |
Family
ID=22212547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB26168/61A Expired GB886422A (en) | 1957-01-25 | 1958-01-24 | Improvements in or relating to data processing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB886422A (en) |
-
1958
- 1958-01-24 GB GB26168/61A patent/GB886422A/en not_active Expired
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