GB8712118D0 - Ttl compatible cmos logic - Google Patents
Ttl compatible cmos logicInfo
- Publication number
- GB8712118D0 GB8712118D0 GB878712118A GB8712118A GB8712118D0 GB 8712118 D0 GB8712118 D0 GB 8712118D0 GB 878712118 A GB878712118 A GB 878712118A GB 8712118 A GB8712118 A GB 8712118A GB 8712118 D0 GB8712118 D0 GB 8712118D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- cmos logic
- ttl compatible
- compatible cmos
- ttl
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT83624/86A IT1204247B (en) | 1986-06-04 | 1986-06-04 | LOGIC CMOS CIRCUIT COMPATIBLE WITH TTL LOGIC CIRCUITS AND WITH LOW CURRENT ABSORPTION IN THE INPUT STAGE |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8712118D0 true GB8712118D0 (en) | 1987-06-24 |
GB2191355A GB2191355A (en) | 1987-12-09 |
GB2191355B GB2191355B (en) | 1989-12-20 |
Family
ID=11323308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8712118A Expired GB2191355B (en) | 1986-06-04 | 1987-05-22 | Ttl compatible cmos logic with low power dissipation in the input stage |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS63153917A (en) |
DE (1) | DE3718769A1 (en) |
FR (1) | FR2599912B1 (en) |
GB (1) | GB2191355B (en) |
IT (1) | IT1204247B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4763021A (en) * | 1987-07-06 | 1988-08-09 | Unisys Corporation | CMOS input buffer receiver circuit with ultra stable switchpoint |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4593212A (en) * | 1984-12-28 | 1986-06-03 | Motorola, Inc. | TTL to CMOS input buffer |
-
1986
- 1986-06-04 IT IT83624/86A patent/IT1204247B/en active
-
1987
- 1987-05-22 GB GB8712118A patent/GB2191355B/en not_active Expired
- 1987-05-29 JP JP62132029A patent/JPS63153917A/en active Pending
- 1987-06-03 FR FR8707764A patent/FR2599912B1/en not_active Expired - Lifetime
- 1987-06-04 DE DE19873718769 patent/DE3718769A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
FR2599912A1 (en) | 1987-12-11 |
GB2191355B (en) | 1989-12-20 |
JPS63153917A (en) | 1988-06-27 |
IT1204247B (en) | 1989-03-01 |
IT8683624A0 (en) | 1986-06-04 |
DE3718769A1 (en) | 1987-12-10 |
GB2191355A (en) | 1987-12-09 |
FR2599912B1 (en) | 1992-12-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0243603A3 (en) | Binary logic circuit | |
GB2193330B (en) | A logic l.s.i. circuit | |
GB2186105B (en) | Multifunction arithmetic logic unit circuits | |
EP0270029A3 (en) | Logic circuit | |
GB2198902B (en) | Cmos logic circuit | |
EP0249128A3 (en) | Ttl technology digital timing unit | |
KR900008803B1 (en) | Logic circuitry | |
EP0266218A3 (en) | Transistor-transistor logic circuit | |
SG26345G (en) | Optical spatial logic arrangement | |
EP0302671A3 (en) | Logic circuit | |
GB8712118D0 (en) | Ttl compatible cmos logic | |
EP0239168A3 (en) | Arithmethic logic circuit | |
GB2213321B (en) | High-speed cmos ttl semiconductor device | |
AU8158687A (en) | Logic toy | |
GB2191302B (en) | Optical logic | |
GB2188504B (en) | Cmos single clock logic arrangement | |
GB8717150D0 (en) | Emmitter coupled logic devices | |
AU591812B2 (en) | Logic voting-circuit | |
GB8609906D0 (en) | Undergarments | |
GB8715201D0 (en) | Logic circuits | |
CS319686A1 (en) | Zapojeni dynamicke logicke sondy ecl s pameti | |
GB2193004B (en) | Optical logic device | |
PL263039A1 (en) | Logic game | |
GB8602229D0 (en) | Logic devices | |
HUT45408A (en) | Round symmetric logic toy |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20030522 |