GB2191355B - Ttl compatible cmos logic with low power dissipation in the input stage - Google Patents

Ttl compatible cmos logic with low power dissipation in the input stage

Info

Publication number
GB2191355B
GB2191355B GB8712118A GB8712118A GB2191355B GB 2191355 B GB2191355 B GB 2191355B GB 8712118 A GB8712118 A GB 8712118A GB 8712118 A GB8712118 A GB 8712118A GB 2191355 B GB2191355 B GB 2191355B
Authority
GB
United Kingdom
Prior art keywords
low power
input stage
power dissipation
cmos logic
ttl compatible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8712118A
Other versions
GB8712118D0 (en
GB2191355A (en
Inventor
Carlo Dallavalle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Microelettronica SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Microelettronica SpA filed Critical SGS Microelettronica SpA
Publication of GB8712118D0 publication Critical patent/GB8712118D0/en
Publication of GB2191355A publication Critical patent/GB2191355A/en
Application granted granted Critical
Publication of GB2191355B publication Critical patent/GB2191355B/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
GB8712118A 1986-06-04 1987-05-22 Ttl compatible cmos logic with low power dissipation in the input stage Expired GB2191355B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT83624/86A IT1204247B (en) 1986-06-04 1986-06-04 LOGIC CMOS CIRCUIT COMPATIBLE WITH TTL LOGIC CIRCUITS AND WITH LOW CURRENT ABSORPTION IN THE INPUT STAGE

Publications (3)

Publication Number Publication Date
GB8712118D0 GB8712118D0 (en) 1987-06-24
GB2191355A GB2191355A (en) 1987-12-09
GB2191355B true GB2191355B (en) 1989-12-20

Family

ID=11323308

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8712118A Expired GB2191355B (en) 1986-06-04 1987-05-22 Ttl compatible cmos logic with low power dissipation in the input stage

Country Status (5)

Country Link
JP (1) JPS63153917A (en)
DE (1) DE3718769A1 (en)
FR (1) FR2599912B1 (en)
GB (1) GB2191355B (en)
IT (1) IT1204247B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763021A (en) * 1987-07-06 1988-08-09 Unisys Corporation CMOS input buffer receiver circuit with ultra stable switchpoint

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593212A (en) * 1984-12-28 1986-06-03 Motorola, Inc. TTL to CMOS input buffer

Also Published As

Publication number Publication date
JPS63153917A (en) 1988-06-27
FR2599912B1 (en) 1992-12-18
FR2599912A1 (en) 1987-12-11
DE3718769A1 (en) 1987-12-10
IT8683624A0 (en) 1986-06-04
GB8712118D0 (en) 1987-06-24
GB2191355A (en) 1987-12-09
IT1204247B (en) 1989-03-01

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20030522