GB851614A - Improvements in or relating to pulse communication systems - Google Patents

Abstract

851,614. Pulse modulation systems. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Jan. 22, 1959 [Jan. 22, 1958], No. 2162/58. Class 40(5). A synchronizing arrangement for a pulse communication system, particularly a multiple p.c.m. or p.a.m. system employs a synchronizing signal occurring once each frame in a sequence in which adjacent synchronizing signals are in a different one of two states, e.g. a pulse or no pulse; or one of two specified pulse amplitudes, and at the receiver means are provided for sampling the incoming pulse train once each frame and for altering the period between samples if the pulses sampled are not in the correct sequence over a period which is longer than a predetermined time. A pulse code modulation system is described in which the synchronizing signals are alternate pulses of opposite polarity, Fig. 2 (a) signifying "ones" and "zeros", the binary information code being made up from similar pulses. The incoming pulse train is applied to a pulse repetition extractor 6, Fig. 1, which produces an output pulse for every pulse position, the output pulses being applied to a counter 8 which produces an output pulse at the frame repetition frequency, each of these latter pulses being used to open the gate or clamp 4 as that when the system is synchronized, every synchronizing pulse is let through to trigger 16. Trigger 16 is turned alternately "off" and "on" by the synchronizing pulses and the output, which is of the form shown in Fig. 2 (c), is differentiated (Fig. 2d) and rectified (Fig. 2e) at 18 and finally applied to a gate 12. Counter 8 also applies its output pulses to gate 12 through delay 10 which compensates for the delay in elements 4, 16, 18. Without timed amplifier 20, gate 12 receives two simultaneous pulses each frame and remains closed. If synchronism is lost, a frame occurs when trigger 16 does not change over and no pulse is applied to gate 12 over line 22. The pulse from delay 10 is thus fed back over line 14 to alter the count of counter 8. The position of the sampled pulse is altered each time the sampled pulses fail to occur in the correct sequence. This however may occur when the system is synchronized, due to fading or interference, and so to prevent unnecessary loss of information amplifier 20 is included and is tuned to half the frame frequency. When the amplifier is giving the full output, it holds gate 12 closed, and the failure of trigger 16 to change over for a few frame periods will not cause appreciable delay in the amplifier output, thus the period between samples is not altered until it is certain that synchronism is lost. A preferred embodiment is shown in Fig. 4 which is a modification of Fig. 1. The differ- and rectifier 18 controls a sawtooth generator 19 whose output is shown as waveform b in Fig. 5. Chain line a represents the rectified output of amplifier 20, and the sawtooth waveform is prevented from falling below the level a by the action of the pulse former 21. Line c shows the output voltage of pulse former 21, and when waveform b falls below this level the output of pulse former 21 also drops and a correction pulse is applied to counter 8.