GB847121A - Improvements in or relating to electrical calculating circuits - Google Patents
Improvements in or relating to electrical calculating circuitsInfo
- Publication number
- GB847121A GB847121A GB1963757A GB1963757A GB847121A GB 847121 A GB847121 A GB 847121A GB 1963757 A GB1963757 A GB 1963757A GB 1963757 A GB1963757 A GB 1963757A GB 847121 A GB847121 A GB 847121A
- Authority
- GB
- United Kingdom
- Prior art keywords
- gates
- pulse
- gate
- channel
- signal generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M17/00—Prepayment of wireline communication systems, wireless communication systems or telephone systems
- H04M17/02—Coin-freed or check-freed systems, e.g. mobile- or card-operated phones, public telephones or booths
- H04M17/023—Circuit arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computer Security & Cryptography (AREA)
- Signal Processing (AREA)
- Prepayment Telephone Systems (AREA)
- Meter Arrangements (AREA)
Abstract
847,121. Coin-freed systems. GENERAL ELECTRIC CO. Ltd. Aug. 20, 1958 [June 21, 1957], No. 19637/57. Class 40 (4). [Also in Group XIX] A multiplex adding and subtracting arrangement particularly adapted for use in pre-payment telephone call timing consists of a number of binary counting stages (of which the first, least significant, three are shown in Fig. 1) each comprising a number of " and " gates (5, 21), " or " gates (15, 24) and." inhibit " gates (8, 18) and a delay line 12 (which may be magnetostrictive, mechanical such as of mercury or quartz, or a magnetic drum) providing a delay of 100 bit periods so that 100 accumulated totals may be stored in the lines 12, 13, 14, ... where they circulate unchanged through gates 15, 18; 16, 19, . . . in the absence of pulse inputs at 1, 2 or 11. Considering one of these totals, it will be increased by one by a pulse received at 1 at the appropriate time (as the bits of the stored number are simultaneously leaving the delay lines) since if no pulse (representing a 0) is leaving 12, gate 5 will be closed and gate 18 open so that a pulse (representing a 1) is entered in 12 through 15 and 18, and if a pulse is leaving 12, gate 5 is opened to close gate 18 through 24 and register a 0, and pass the input pulse to the next highest stage. The total will be decreased by 1 by an input pulse at 2 by similar action of gates 8, 21, 9, 22, &c. Lines 27, 28, 29, . . . allow read-out, and a pulse on line 11 acts through gates 24, 25, 26, ... to re-set the total to zero by closing gates 18, 19, 20, .... Fig. 2 shows the application of the Fig. 1 counter to a telephone call timer for use in an automatic telephone exchange. A signal generator (such as that described in Specification 824,352) provides output pulses for any one (or more) of the 100 channels of the multiplex counter of Fig. 1, the rate of production of such pulses for the channel being determined by the distance of the telephone call (as determined by the routing digits dialled) to which the channel is allocated. Coins inserted by the caller supply a number of pulses corresponding to their value to terminal 1, and signal generator pulses applied to 2 successively reduce the number registered until it reaches zero, and then 1 1 1 1 . . ., which when read out on output lines 27, 28, 29,... acts through " and " gate 30 to store a " 1 " in the appropriate channel position of delay line 33, (forming part of a recirculating store) which when received on line 37 disables through inhibit gate 34 the signal generator for that channel and provides a signal for the caller that more coins must be inserted; if they are the " 1 " stored in 33 will be erased by inhibit gate 32 and the signal generator will thus again operate on the channel, the signal will be discontinued, and the Fig. 1 counter will count down the further payment as before. Specification 816,487 also is referred to.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1963757A GB847121A (en) | 1957-06-21 | 1957-06-21 | Improvements in or relating to electrical calculating circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1963757A GB847121A (en) | 1957-06-21 | 1957-06-21 | Improvements in or relating to electrical calculating circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
GB847121A true GB847121A (en) | 1960-09-07 |
Family
ID=10132681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1963757A Expired GB847121A (en) | 1957-06-21 | 1957-06-21 | Improvements in or relating to electrical calculating circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB847121A (en) |
-
1957
- 1957-06-21 GB GB1963757A patent/GB847121A/en not_active Expired
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