GB844894A - Improvements in or relating to electrical calculator apparatus - Google Patents
Improvements in or relating to electrical calculator apparatusInfo
- Publication number
- GB844894A GB844894A GB1134/58A GB113458A GB844894A GB 844894 A GB844894 A GB 844894A GB 1134/58 A GB1134/58 A GB 1134/58A GB 113458 A GB113458 A GB 113458A GB 844894 A GB844894 A GB 844894A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- gate
- circuit
- signals
- total
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
- G06Q10/08—Logistics, e.g. warehousing, loading or distribution; Inventory or stock management
- G06Q10/087—Inventory or stock management, e.g. order filling, procurement or balancing against orders
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Business, Economics & Management (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Economics (AREA)
- Finance (AREA)
- Development Economics (AREA)
- Accounting & Taxation (AREA)
- Entrepreneurship & Innovation (AREA)
- Human Resources & Organizations (AREA)
- Marketing (AREA)
- Operations Research (AREA)
- Quality & Reliability (AREA)
- Strategic Management (AREA)
- Tourism & Hospitality (AREA)
- General Business, Economics & Management (AREA)
- Complex Calculations (AREA)
Abstract
844,894. Digital electric calculating-apparatus. WESTINGHOUSE ELECTRIC CORPORATION. Jan. 13, 1958 [Jan. 23, 1957], No. 1134/58. Class 106 (1). In an electrical binary adding and subtracting device digit-representing signals are applied to first, second, and third OR circuits whose outputs are connected to different inputs of a first AND circuit to provide a carry signal, the output of the second OR circuit being connected also to a fourth OR circuit which controls a second AND circuit, the latter and a third AND circuit which is subject to the input signals, controlling a fifth OR circuit so as to provide a sum signal. General. The adding and subtracting device 36, Fig. 1, is described as part of a system for keeping account of workpieces 18 entering and leaving a warehouse 20. When the conveyer 16 comes to rest a binary counter 26 and a temporary register 46 are cleared. When it is restarted a switch 24, operated by each passing workpiece, steps on the counter 26 to keep count of the number of workpieces delivered. At the end of the delivery a sequence control 32 gates the number registered in the counter 26 to the adding and subtracting device 36 and also causes the total held in a register 48 to be entered. A signal from a switch 38, responsive to the direction of movement of the conveyer, determines whether the last count is to be added or subtracted from the total. The result is passed into a temporary register 46 before replacing the previous entry in the total register 48. Add-subtract device. The binary numbers from the counter 26 and total register 48 are added or subtracted in parallel mode (Fig. 3, not shown), each of the add/subtract circuits being arranged as shown in Fig. 2. The logical elements used are of the type using A.C. voltages and therefore phase-shift devices are interposed as required. Number digit signals A, B are applied on lines 58 and 60, and carry input signals C enter on line 64. The signal derived from the switch 38 when the count is to be added appears on line 62, opening an AND gate 72 and so passing the unchanged B signals to the adding circuit. The absence of this signal signifies subtraction and in this case the B signals are complemented by a device 80 before reaching the adding circuit. The input signals are applied in pairs to first, second and third OR gates 82, 86 and 68 and the outputs of the latter are combined in a first AND gate 70 to provide a carry signal on line 90. The output from AND gate 70 is also used to provide a complemented signal to a second AND gate 96 which also receives an A+B+C signal from a fourth OR gate 94. The output from gate 96 together with the output signal ABC from a third AND gate 98 are combined in a fifth OR gate 100 to provide a sum signal. Arrangements for dealing with the " fugitive one " and for economizing in the higher order circuits where provision is necessary only for the carry and the total signals, are also described.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US844894XA | 1957-01-23 | 1957-01-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB844894A true GB844894A (en) | 1960-08-17 |
Family
ID=22185282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1134/58A Expired GB844894A (en) | 1957-01-23 | 1958-01-13 | Improvements in or relating to electrical calculator apparatus |
Country Status (3)
Country | Link |
---|---|
BE (1) | BE564141A (en) |
FR (1) | FR1198508A (en) |
GB (1) | GB844894A (en) |
-
0
- BE BE564141D patent/BE564141A/xx unknown
-
1958
- 1958-01-13 GB GB1134/58A patent/GB844894A/en not_active Expired
- 1958-01-22 FR FR1198508D patent/FR1198508A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR1198508A (en) | 1959-12-08 |
BE564141A (en) |
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