GB829794A - Improvements in or relating to counter devices - Google Patents

Improvements in or relating to counter devices

Info

Publication number
GB829794A
GB829794A GB859957A GB859957A GB829794A GB 829794 A GB829794 A GB 829794A GB 859957 A GB859957 A GB 859957A GB 859957 A GB859957 A GB 859957A GB 829794 A GB829794 A GB 829794A
Authority
GB
United Kingdom
Prior art keywords
cores
abc
state
pulses
stages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB859957A
Inventor
Eric Douglas Mcconnell
William James Rowley Clark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Marconis Wireless Telegraph Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconis Wireless Telegraph Co Ltd filed Critical Marconis Wireless Telegraph Co Ltd
Priority to GB859957A priority Critical patent/GB829794A/en
Publication of GB829794A publication Critical patent/GB829794A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/76Pulse counters comprising counting chains; Frequency dividers comprising counting chains using magnetic cores or ferro-electric capacitors

Abstract

829,794. Circuits of bi-stable magnetic elements. MARCONI'S WIRELESS TELEGRAPH CO. Ltd. Jan. 20, 1958 [March 15, 1957], No. 8599/57. Class 40 (9). [Also in Group XIX] A counter or frequency divider comprises a plurality of counter stages each consisting of a magnetic core counting ring and has auxiliary cores acting to transfer pulses between the counter stages. As shown, Fig. 2, a binary counter comprises stages such as A each comprising two cores A1, A2, coupled bidirectionally by R-C delay networks A11, A13, are interconnected by transfer cores ABC. Input pulses at the terminals CPN are supplied at a frequency nF, where n is the number of stages, to all the transfer cores such as ABC, and to a frequency-divider N, F being the rate at which the first stage A is supplied with pulses. Initially the first cores A1 of each stage are in the " 1 " state, and the second cores A2 are in the " O " state, the auxiliary cores ABC being in the " O " state. Pulses supplied to the terminals CPN tend to switch the cores to the " O " state. In a modification (Fig. 3, not shown), the auxiliary cores ABC and an additional input core for the first stage are fed sequentially from a circulating stepping register.
GB859957A 1957-03-15 1957-03-15 Improvements in or relating to counter devices Expired GB829794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB859957A GB829794A (en) 1957-03-15 1957-03-15 Improvements in or relating to counter devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB859957A GB829794A (en) 1957-03-15 1957-03-15 Improvements in or relating to counter devices

Publications (1)

Publication Number Publication Date
GB829794A true GB829794A (en) 1960-03-09

Family

ID=9855586

Family Applications (1)

Application Number Title Priority Date Filing Date
GB859957A Expired GB829794A (en) 1957-03-15 1957-03-15 Improvements in or relating to counter devices

Country Status (1)

Country Link
GB (1) GB829794A (en)

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