GB814183A - Improvements in or relating to automatic telecommunication exchanges - Google Patents

Abstract

814,183. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. May 3, 1957 [May 8, 1956], No. 14293/56. Class 40 (4). An exchange has a time division multiplex highway over which speech channels are connected at a first repetition frequency and supervisory channels, are connected at a second repetition frequency which is a submultiple of the first frequency. The exchange utilizes a time division multiplex system with a first switching stage over which a calling line is extended to an inlet to the system, means which in response to the reception of a wanted subscriber's designation marks that subscriber's line, a second switching stage over which the marked subscriber's line is extended to an outlet of the system, and a control circuit which selects an idle multiplex channel to connect the inlet and outlet. The inlets and outlets may be connected by a single multiplex highway or may be divided into groups, each group being served by a separate multiplex highway. As shown in Figs. 2 and 3, when a subscriber SS1 initiates a call, a calling line marker LM is seized causing all other such markers to be locked out and causing the calling line circuit LC1 to be extended over co-ordinate switch TCA to a free link IL. The marker LM ensures that static electrical circuits cope with one call at a time. The switch TCA may be a static electrical switch, a time division multiplex system, or a mechanical switch such as a cross-bar switch, in which case a control device is included to permit release of LM and allow switch TCA to operate at its own speed. The seized link IL takes a free register REG into use.over a selector RH and dial tone is returned to the subscriber who dials the wanted subscriber's designation for storage in REG. A call distributer CD ensures that only one register is in use for call setting at any one time and causes the transference of information in REG to a line marker CLM, serving the whole exchange, while allowing a predetermined interval within which the call may be established, failing which busy tone is returned. The line marker CLM over busbars AB, CD, marks the gate circuit LMG of the wanted subscriber, who for convenience of illustration is assumed to be the subscriber SS1, and sets his line circuit LC1 to a called condition in which it is extended over switch TCB to seize a final link FL. The identities of the seized links 1L and FL are recorded in a control circuit RS ; the link 1L being one of a group connected to a multiplex highway HA1 over gates GA, while the link FL is one of a group connected to a multiplex highway HB1 over gates GB; highways HA2-HAN serving further groups of inlets, and highways HB2-HBN serving further groups of outlets, each highway HA being connectible to a highway HB over a cross-point gate GC. For the links 1L and FL the control circuit RS selects a channel time period idle in both highways HA1, HB1, and thereafter repeatedly opens the gates GA1, GC11, GB1, during this period. Repeated operation of the gates may be effected by having a set of stores equal in number to the number of time positions in the multiplex cycle, for each set of gates GA, GB, and GC. Alternatively, each gate may be provided with its own store registering the times at which it should be open. As shown in Fig. 7, each gate, such as GA1 to GAM, is provided with a store S1 to SM, each store forming one row in a storage matrix having as many columns as there are channel time periods during each of which a characteristic column wire is subjected to a read-out pulse followed by a half-write pulse. The cells of each store may be holes in a slab of ferrite material or separate magnetic cores. A connection is originated by the application of a pulse from the control circuit RS to a gate GD, such as is shown for the store S1 associated with the multiplex gate GA1, during the selected channel time period. The pulse, amplified at AGA1, enables the multiplex gate GA1 and enables a gate GE to which half-write pulses are repeatedly applied, thereby energizing the row winding in coincidence with a column wire. An element of S1 therefore turns over and is read out at this channel time during each subsequent multiplex cycle to enable gate GA1 over amplifier AGA1 the output of which also automatically re-writes the information by enabling gate GE. Release of the connection is effected by inhibiting gate GE over a lead IC. An arrangement by which a multiplex channel may be selected between the first and final links IL and FL of Figs. 2 and 3, is shown in Figs. 4, 5 and 6. The gate GA1 between link IL and multiplex highway HA1 is associated with a store S1 and amplifier AGA1, gate GB1 between link FL and multiplex highway HB1 is associated with a store S3 and amplifier AGB1, while the highways HA1, HB1 are connectible over gate GC11 associated with store S2 and amplifier AGC 11. Seizure of any first link of the group associated with highway HA1 enables gate A1SC by applying a mark over mixing gate A10 so that the outputs of the amplifiers AGA of the group, indicating busy channel time periods in highway HA1, are applied to inhibit a comparator gate C. Seizure of a final link similarly enables gate B1SC to apply the outputs of amplifiers AGB to inhibit comparator gate C. An idle channel time period in both highways HA1, HB1, implies no output from either group of amplifiers AGA, AGB, so that gate C is not inhibited and passes a pulse from a source of multiplex pulses PG and over gates L10 registers the idle period in stores S1, S3, to connect the links to their highways, while over gate GC110 the period is registered in store S2 to connect the highways. To prevent double connections a bi-stable circuit SF is triggered by the PG pulse to immediately re-inhibit comparator gate C. Release is initiated by supervisory signals indicating calling subscriber's release which cause first link IL to open gate L1RC so that the next output of AGA1 is fed back to inhibit re-write in store S1, and passed over lines ha1, hb1, to inhibit re-write in stores S2 and S3. Release of the connector switches and links follows after the manner described in Specification 794,812. A path for supervisory signals is provided by the provision of an extra pulse in each multiplex cycle, the (n + 1 )th pulse of an n channel system being allocated to each one of the n channels in turn during successive cycles. Thus the column wires of a store would be pulsed once every cycle and additionally by the (n+ 1)th pulse every nth cycle. The supervisory channel is taken from a multiplex highway to a link circuit, as shown in Fig. 8, by allowing enablement of the speech gate GA1 only during the n pulses of a channel over lead a while allowing enablement of an additional gate GAS during the (n+ 1)th pulse over lead b, the supervisory intelligence being handled by the link circuit. Supervisory channels may be provided by an alternative method in which one complete multiplex cycle in every thousand is set aside for supervision which for a 10 kc/s. cycle frequency gives supervision at 10 c.p.s. If the supervisory intelligence is handled by equipment common to a group of link circuits, only one additional gate is required for each highway; the intelligence being diverted during the (n+ 1)th pulses to a storage matrix (Fig. 9, not shown). Specifications 765,681, 791,933 and 813,580 also are referred to. Referencehas been directed by the Comptroller to Specification 781,561.