GB723774A - Arrangement for shifting the multiplicand in a calculating machine - Google Patents
Arrangement for shifting the multiplicand in a calculating machineInfo
- Publication number
- GB723774A GB723774A GB14809/51A GB1480951A GB723774A GB 723774 A GB723774 A GB 723774A GB 14809/51 A GB14809/51 A GB 14809/51A GB 1480951 A GB1480951 A GB 1480951A GB 723774 A GB723774 A GB 723774A
- Authority
- GB
- United Kingdom
- Prior art keywords
- trigger
- triggers
- register
- multiplicand
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/498—Computations with decimal numbers radix 12 or 20. using counter-type accumulators
- G06F7/4983—Multiplying; Dividing
- G06F7/4985—Multiplying; Dividing by successive additions or subtractions
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Control By Computers (AREA)
- Complex Calculations (AREA)
Abstract
723,774. Digital electric calculating-apparatus. COMPAGNIE DES MACHINES BULL. June 21, 1951 [June 26, 1950], No. 14809/51. Class 106 (1). In an electronic machine for automatically performing the multiplication of two decimal numbers, a registering arrangement comprises a multiplicand register adapted to register digits of successive decimal orders on respective groups of units corresponding to predetermined coded values, groups of switching devices each associated with one register group, a first pulse generator for applying a clearing pulse to each register group, and a second generator for applying to each group of switching devices a differently-timed pulse to shift to the associated register group the digit registered on an adjacent group. The multiplicand register shown comprises five decimal denominations U, D, C, M, DM, each consisting of four hard-valve trigger pairs 20 representing coded values 1, 2, 4, 8. Each trigger, except in the highest denomination DM, applies an output potential over a line such as 28 to a gate circuit 26 so that if it is in the " on " state (represented by shading of the lower portion and of an associated neon indicating lamp 21) the gate will be open (represented by horizontal instead of vertical lines) to allow an operating pulse to be applied from a distributer D1 to the corresponding trigger in the next higher denomination. The distributer supplies pulses to the gates of denominations M, C, D, U in that order, which pulses are timed to be interspersed with, and a half-step in advance of, resetting pulses from a distributer D2. In operation, the distributers are operated to effect denominational shift after each multiplication of the multiplicand by a digit of the multiplier. The multiplication may be effected by repeated addition employing an electronic accumulator similar to that described in Specification 679,993. In a modification (Figs. 3a-3c, not shown) in which shift occurs simultaneously in all denominations, the distributers are omitted and each valve-registering trigger (A) has a second trigger (B) associated therewith. When resetting pulses are applied simultaneously to all triggers (A), the number registered is transferred to triggers (B), and on the subsequent resetting of triggers (B) the number is sent to the corresponding triggers (A) of next higher denomination.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR862686X | 1950-06-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB723774A true GB723774A (en) | 1955-02-09 |
Family
ID=9342944
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB14809/51A Expired GB723774A (en) | 1950-06-26 | 1951-06-21 | Arrangement for shifting the multiplicand in a calculating machine |
Country Status (5)
Country | Link |
---|---|
BE (1) | BE503716A (en) |
DE (1) | DE862686C (en) |
FR (1) | FR1020970A (en) |
GB (1) | GB723774A (en) |
NL (2) | NL83229C (en) |
-
0
- NL NL6818690.A patent/NL161734B/en unknown
- NL NL83229D patent/NL83229C/xx active
- BE BE503716D patent/BE503716A/xx unknown
-
1950
- 1950-06-26 FR FR1020970D patent/FR1020970A/en not_active Expired
-
1951
- 1951-06-07 DE DEC4308A patent/DE862686C/en not_active Expired
- 1951-06-21 GB GB14809/51A patent/GB723774A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR1020970A (en) | 1953-02-12 |
BE503716A (en) | |
DE862686C (en) | 1953-01-12 |
NL83229C (en) | |
NL161734B (en) |
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