GB723648A - Improvements in or relating to electrical counting and like devices - Google Patents

Abstract

723,648. Multi-stable state circuits. STANDARD TELEPHONES & CABLES, Ltd. July 17, 1951, No. 16933/51. Class 40 (6). A pulse frequency divider comprises two counting chains in which pairs of elements, one from each chain, are interconnected in dependence upon the divisor required. The Figure shows a divider in which the negative-going pulses to be divided are applied at the terminal " Input " to the common trigger electrode of a first gas-filled multi-gap sequence tube A of the type described in Specification 692,415 [Group XL (a)], the cathodes KA1-KA10 of which are cross-connected via coincidence gates MA1, MB10, MR1, MA10, MB1, MR10 to a second sequence tube B. Initially cathodes KA1 and KB1 are discharging and each input pulse applied causes the discharge of the first tube A to step forward one gap so that on the ninth pulse gap 10 fires and as cathode KB1 is discharging rectifiers MA10, MB1 are blocked and a positive pulse is applied via rectifier MR10 to the grid of amplifier valve VI. The resulting negative pulse at the anode of valve V1 is applied to the negative output terminal and to the trigger electrode of tube B, the discharge in which steps on to gap 2. The tenth input pulse causes gap 1 in tube A to re-fire and the discharge progresses along tube A until on the eighteenth pulse gap 9 fires and as gap 2 of tube B is firing a pulse is applied via rectifier MR9 (not shown) to valve V1 and then to the negative output terminal. The cycle thus continues with coincidence occurring one step earlier in each cycle so that division by nine is obtained. If division by eight is required then the coincidence is stepped forward two steps per cycle by interconnecting KA10, KB1; KA8, KB2; KA6, KB3, &c. Thus by interconnecting pairs of elements in a predetermined order, division by any divisor up to 19 may be obtained.