GB2624846A

GB2624846A - A method of forming a semiconductor or dielectric layer on a substrate

Info

Publication number: GB2624846A
Application number: GB2212822.7A
Authority: GB
Inventors: Guiney Ivor; Dixon Sebastian; Morris Oliver
Original assignee: Paragraf Ltd
Current assignee: Paragraf Ltd
Priority date: 2022-09-02
Filing date: 2022-09-02
Publication date: 2024-06-05
Also published as: GB202212822D0

Abstract

Method of forming a laminate devoid of organic polymer. The method comprises forming a semiconductor (e.g., a II-VI or III-V semiconductor) or dielectric layer on a substrate 100 using epitaxial lateral overgrowth comprising forming a porous layer of graphene 105, preferably a porous monolayer of graphene, on the substrate, and forming a semiconductor or dielectric layer 115, 120 on the substrate and the porous layer of graphene. The porous layer of graphene may be formed by CVD sequentially in-situ in a CVD reaction chamber. The substrate may be separated from the semiconductor or dielectric layer, whereby the porous layer of graphene during separation may remain at least partially on one or both of the substrate and the semiconductor or dielectric layer. One or more further layers may be formed on the semiconductor or dielectric layer. An electronic device (e.g., an opto-electronic device or transistor) comprising the laminate.

Description

A method of forming a semiconductor or dielectric layer on a substrate The present invention relates to a method of forming a semiconductor or dielectric layer on a substrate. More particularly, the method relates to epitaxial lateral overgrowth of the semiconductor or dielectric layer on a substrate having thereon a porous graphene layer, preferably a porous graphene monolayer. The present invention also relates to a laminate comprising a substrate, a porous layer of graphene and a semiconductor or dielectric layer, as well as an electronic device comprising the same. The laminate may be particularly suited for manufacturing opto-electronic devices, for example LEDs, and transistors.

Within the field of electronic device manufacture, there remains a need for methods which allow for the integration of high quality semiconductor layers, in particular those based on Group III-V. Epitaxial lateral overgrowth (ELO or ELOG) may also be referred to as lateral epitaxial overgrowth (LEO) and is a technique that aims to improve the crystallinity of such layers. Conventionally, the process involves coating a substrate with a dielectric, typically silicon dioxide or silicon nitride, and patterning the dielectric to form windows or strips which expose the underlying substrate (i.e. a mask). The dielectric layer may be patterned through conventional photolithography techniques. The semiconductor layer may be grown on the substrate patterned with the dielectric layer; for example GaN may be formed by MOCVD or MOVPE.

By selecting appropriate deposition parameters, growth initially occurs only in the window areas on the underlying substrate and growth continues substantially vertically (e.g. along the c-axis) until the semiconductor layer extends above the top of the mask. Silicon dioxide and silicon nitride are conventional dielectric materials for ELO which provide "non-wettable" surfaces such that nucleation and growth of the semiconductor layer does not occur. Once the layer extends above the height of the mask, the semiconductor layer may commence lateral growth (i.e. perpendicular to the c-axis). Growth in this direction can be much faster than the vertical direction. During lateral growth (forming the wing regions), the dislocations tend to follow the faster growth direction and, ideally result in no dislocations along the c-axis. The wing regions eventually coalesce with adjacent regions to form a continuous semiconductor layer.

Graphene is a leading two-dimensional material that has been incorporated in numerous products for its extraordinary electronic properties. Graphene is a well-known allotrope of carbon which consists of a layer of carbon atoms arranged in a two-dimensional honeycomb lattice, optionally doped with heteroatoms. Each carbon atom is covalently bonded with its three nearest neighbours leaving one electron which for the valence band. An undoped monolayer of graphene is a semimetal whereby there is no (or negligible) gap between the valence and conduction bands. The graphene may be doped to either introduce additional electrons or holes.

It has been shown that graphene has a transparent wetness whereby the graphene cannot screen the stronger potential field of the underlying substrate upon which it is provided. This transparency allows for epitaxial growth on its surface, as reported in "Remote epitaxy through graphene enables two-dimensional material-based layer transfer" Kim et al., Nature, 544, 2017, 340-343, "Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene" Kim et al., Nature Communications, 5:4836, 2014, as well as "Polarity governs atomic interaction through two-dimensional materials" Kong et al., Nature Materials, 17, 2018, 999-1004.

US 2010/320445, US 2014/220764, and US 2015/083036 all relate to forming semiconductor layers for electronic devices on a graphene layer on a substrate.

Despite these advances, growth of semiconductor layers such as GaN remains difficult on such surfaces due the lack of dangling bonds at the surface of a two-dimensional material. The screening effect of the graphene may also play an effect for certain substrates. "Multiple epitaxial lateral overgrowth of GaN thin films using a patterned graphene mask by metal organic chemical vapor deposition" Lee et al., J. Apply. Cryst., 53, 2020, 1502-1508, discloses transferring a graphene layer to GaN grown on a sapphire substrate and forming a pattern of holes with a diameter of 2 pm and a period of 4 pm by photolithography and reactive ion etching with oxygen plasma to expose the underlying GaN. ELO of GaN is then performed on the GaN template with hole-patterned graphene by MOCVD. "Demonstration of epitaxial growth of strain-relaxed GaN films on graphene/SiC substrates for long wavelength light-emitting diodes" Yu et al., Light: Science & Applications, 10:117, 2021, discloses a nitrogen-plasma pre-treatment of graphene on a SIC substrate to form C-N related dangling bonds to provide nucleating sites for subsequent epitaxial growth of AIN buffer seeds for a GaN layer.

US 2018/197736 discloses in an embodiment forming a plurality of periodic pinholes in a graphene monolayer on a silicon carbide substrate. The plurality of pinholes are formed by first depositing an porous film such as a photoresist and dry etching the graphene using argon or oxygen plasma. The porous film is then removed and an epitaxial layer is grown on and across the substrate and the surface of the damaged graphene.

The present invention aims to provide a method which results in improved crystallinity of a semiconductor or dielectric layer with reduced defects and dislocations. Such a layer having more ideal properties would be beneficial for use in electronic devices such as LEDs. The present invention also aims to provide a more efficient method which is suitable for the manufacture of large area semiconductor or dielectric layers with improved conformity across the width of the substrate so as to allow for the manufacture of an array of electronic devices with consistent properties.

Accordingly, in a first aspect of the present invention, there is provided a method of forming a semiconductor or dielectric layer on a substrate, the method comprising: providing a substrate having a growth surface; forming a porous layer of graphene, preferably a porous monolayer of graphene, on the growth surface of the substrate; and forming a semiconductor or dielectric layer on the growth surface of the substrate and the porous layer of graphene.

The present disclosure will now be described further. In the following passages, different aspects/embodiments of the disclosure are defined in more detail. Each aspect/embodiment so defined may be combined with any other aspect/embodiment or aspects/embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous. It is intended that the features disclosed in relation to the method may be combined with those disclosed in relation to the laminate (i.e. the graphene-containing laminate), as well as any device incorporating such a laminate structure, and vice versa. Accordingly, the laminate is obtainable by the method and also the method is one suitable for manufacturing the laminate described herein.

Thus, in a further aspect, the present invention provides a laminate comprising: a substrate; a porous layer of graphene, preferably a porous monolayer of graphene, on a surface of the substrate; and a semiconductor or dielectric layer on the surface of the substrate and the porous layer of graphene; wherein the laminate is devoid of organic polymer.

In a further aspect, the present invention provides an electronic device comprising such laminate. Preferably, the electronic device is an opto-electronic device (such as an LED, laser diode or electrooptic modulator) or transistor (such as a High-Electron-Mobility-Transistor (HEMT)).

In the following there is discussed a porous layer of graphene. It is preferred that this is a porous monolayer of graphene or a bilayer of graphene. This is because it is easiest to form the incomplete porous structure required when the number of layers is lowest. For simplicity, reference is made hereafter to "monolayers", but it should be appreciated that in some embodiments this may encompass suitable porous graphene layers having bilayers or even 3 or more layers of graphene around the pores.

In the following there is discussed a semiconductor or dielectric layer. It is most preferred that this layer is a semiconductor layer. For simplicity, reference is made hereafter generally to a semiconductor layer. However, it should be appreciated that in some embodiments this may instead be a dielectric layer. Moreover, depending on the intended application, it is well known that some materials may be classed as either a semiconductor and/or a dielectric. A "traditional" semiconductor material, for example silicon or germanium, may be considered one to have a bandgap greater than 0 eV up to 2 eV, for example from 0.6 to 1.5 eV (where bandgaps are measured at 300 K). These may be known as "small-bandgap" semiconductors. However, it will be appreciated that semiconductor materials may have a greater range of bandgaps, for example up to 5 eV, and even up to 7 eV. Such materials may be known as "wide-bandgap" semiconductors which, in some applications, may be referred to as dielectrics, or even semi-insulators. Accordingly, a semiconductor layer is preferably formed of a material having a bandgap of greater than 0 eV up to 7 eV, for example greater than 0 eV up to 5 eV, preferably from 0.6 eV to 7 eV, such as from 0.6 eV to 5 eV. Materials having a bandgap greater than 7 eV are therefore generally known as dielectric materials.

The method first comprises providing a substrate having a growth surface. The substrate may be any conventional substrate that is suitable for use in the electronics industry. Such substrates may be referred to as wafers and are thin slices of semiconductor or dielectric material and may be used for microfabrication processes (i.e. they are non-metallic substrates). In some embodiments, the substrate consists of a single material, such as those described herein and one surface of the substrate provides a growth surface. In other embodiments, the substrate may consist of two or more of such materials and may itself be a laminate substrate. For example, the substate may consist of two layers. A first layer may be referred to as a support layer which may itself be a commercially available substrate/wafer, for example, a silicon wafer is preferred though any of the materials described herein may be suitable as a support. Generally, a support layer may be substantially thicker than a second layer formed thereon. The second layer may be referred to as an epitaxial layer and may be grown by epitaxy on the support layer and the epitaxial layer provides the growth surface of the substrate for use in the present method. In some embodiments the second layer may be transferred onto the support layer. The second layer may also be any of the materials described herein.

The substrate may also be a CMOS wafer which may be silicon based and have associated circuitry embedded within the substrate. A substrate may also comprise one or more layers (for example, regions or channels of embedded waveguide materials such as silicon nitride suitable for electro-optic modulators).

Preferably, the growth surface upon which the porous monolayer of graphene is formed is silicon (Si), germanium (Ge), silicon carbide (SiC), silicon nitride (Si3N14), silicon dioxide (Si02), sapphire (A1203), aluminium gallium oxide (AGO), hafnium dioxide (Hf02), zirconium dioxide (Zr02), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgA1204), yttrium orthoaluminate (YAI03), yttrium oxide (Y203), strontium titanate (SrTiO3), cerium oxide (0e203), scandium oxide (Sc203), erbium oxide (Er203), magnesium difluoride (MgF2), calcium difluoride (CaF2), strontium difluoride (SrF2), barium difluoride (BaF2), scandium trifluoride (ScF3), or a Group IV, II-VI or III-V material (preferably semiconductor). Most preferably the growth surface is crystalline. Examples of suitable materials include diamond (i.e. cubic carbon; bandgap of about 5.5 eV), hexagonal boron nitride (h-BN; bandgap of about 5.2 eV) and cubic boron nitride (c-BN; bandgap of about 6.4 eV).

Examples of Group III-V semiconductors include aluminium nitride (AIN; bandgap of about 6.0 eV), gallium nitride (GaN; bandgap of about 3.4 eV), and indium nitride (InN; bandgap of about 0.7 eV) and examples of Group II-VI semiconductors include zinc selenide (ZnSe; bandgap of about 3.7 eV) and cadmium telluride (CdTe; bandgap of about 1.5 eV).

Preferably, the group III element is selected from one or more of the group consisting of B, Al. Ga and In, and the group V element is selected from or more of the group consisting of N, P, As and Sb, preferably N or P. Group III-V semiconductors may be binary, ternary or quaternary semiconductors. By way of example, suitable semiconductors include GaN, InGaN, GaP, AlGaP, and AlGaInP. Such materials and their appropriate stoichiometries of each element are well known to those skilled in the art. The present invention is particularly suited to forming semiconductor layers formed of Group II-VI or Group III-V semiconductors as described for the substrate. In some preferred embodiments, the semiconductor layer is formed of the same semiconductor as the semiconductor the growth surface of the substrate is formed of.

Preferably, the group IV element is selected from one or more of the group consisting of C, Si and Ge. Ge and AIN are two examples of particularly preferred materials since the inventors have found that these are especially well suited for the formation of high quality graphene thereon so as to afford a higher quality semiconductor layer as described herein. As such, substrates of silicon with epitaxial germanium or aluminium nitride are also preferred substrates. In some embodiments, it is preferred that the growth surface of the substrate does not comprise C and/or Si, particularly SiC, since such substrate surfaces are believed to have greater covalency with the graphene which is formed thereon which can introduce defects into the graphene (due to the formation of C-C and/or C-Si bonds).

As will be appreciated, group II, Ill, IV, V and VI elements refer to elements of groups 12, 13, 14, 15 and 16 of the periodic table.

In some preferred embodiments, the substrate comprises a first layer (a support) formed of silicon or sapphire, and a second layer formed of a Group III-V semiconductor. In other embodiments, the substrate comprises a sapphire support and a second layer formed of a group IV element such as silicon and/or germanium.

The thickness of the substrate is not limited and may be any conventional thickness as is typical for electronic device substrates. Typically, the thickness of such substrates are 300 microns to 2 mm

B

thick. In some preferred embodiments, a thin semiconductor laminate, and ultimately a thin electronic device, can be obtained by reducing the thickness of the substrate by thinning (for example, as described in GB 2603905). Preferably such thinning is carried out on a silicon substrate having a second layer upon which the porous graphene monolayer is formed. Thinning may be carried out by etching with an etchant and/or grinding (preferably where etching follows a preliminary grinding). The substrate thickness after thinning may be 200 microns or less, preferably 100 microns or less. Such a step may also be referred to as "wafer backgrinding". In a similar, yet alternative process, as described herein, lift-off may be used to remove the entire substrate from the semiconductor layer.

The method comprises forming a porous monolayer of graphene on the growth surface of the substrate. As used herein, forming may be considered synonymous with synthesising, depositing, producing and growing. On also means directly on such that the method involves forming the graphene directly on the growth surface of the substrate. Therefore, as will be appreciated, the method does not encompass forming graphene elsewhere and transferring the graphene onto the growth surface of the substrate. For example, monolayer graphene is often formed on catalytic metal substrates (such as in the background art discussed herein). Organic polymer such as PMMA is then coated onto the graphene layer. The metallic substrate, typically copper or nickel, is then etched away using an etchant such as FeCla and the PMMA coated graphene is transferred onto the desired final substrate. The organic polymer may then be dissolved. However, this invariably leaves organic polymer residues which are unavoidable and the use of harsh etchants and solvents also lead to graphene damage. The mechanical process of the transfer can also introduce physical defects such as wrinkles and ripples. The present process avoids these problems.

One particularly preferred method for forming the graphene on the growth surface of the substrate is CVD. CVD refers generally to a range of chemical vapour deposition techniques, each of which involve vacuum deposition to produce thin film materials such as two-dimensional crystalline materials like graphene. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. CVD as described herein is intended to refer to thermal CVD such that the formation of graphene from the decomposition of a carbon-containing precursor is the result of the thermal decomposition of said carbon-containing precursor.

The graphene being grown by CVD directly on the substrate therefore avoids physical transfer processing. The physical transfer of graphene, usually from copper substrates, introduces numerous defects which negatively impacts the physical and electronic properties of graphene. As such, a person skilled in the art can readily ascertain whether the graphene, and by extension a graphenecontaining semiconductor laminate as described herein is one comprising a CVD-grown graphene monolayer that has been grown directly on the substrate. This may be determined using conventional techniques in the art such as atomic force microscopy (AFM) and energy dispersive X-ray ([DX) spectroscopy. The porous monolayer of graphene is devoid of metal (e.g. copper) contamination and devoid of transfer polymer residues by virtue of the complete absence of these materials in the process. Furthermore, such processing is generally not suitable for large scale manufacture (such as on CMOS substrates in fabrication plants). Unintentional doping, particularly from the catalytic metal substrates together with the etching solutions, also results in the production of graphene which is not sufficiently consistent from sample to sample as is required for commercial production.

Preferably, the method involves forming graphene by thermal CVD such that decomposition is a result of heating the carbon-containing precursor. Preferably, the temperature of the growth surface during CVD is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. The inventors have found that such temperatures are effective for providing graphene growth directly on the materials described herein by CVD. In some embodiments, the growth temperature preferably does not exceed 950°C, for example where the substrate, or a portion thereof such as the growth surface, is formed of germanium.

Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber. In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm. even more preferably less than 10 mm, between the surface of the substrate and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the substrate and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the substrate surface (i.e. the surface of the metal oxide layer). Accordingly, such an embodiment involves a "vertical" arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the substrate surface (i.e. the growth surface).

The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C. For the avoidance of doubt, the addition of precursor at a temperature above ambient does not constitute heating the chamber, since it would be a drain on the temperature in the chamber and is responsible in part for establishing a temperature gradient in the chamber.

Preferably, a combination of a sufficiently small separation between the substrate surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the substrate to with a decomposition range of the precursor, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017/029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform graphene directly on non-metallic substrates, preferably across the entire growth surface of the substrate. Instead of maximising the thermal gradient, is may be preferred to form graphene by CVD with a greater separation between inlet and the growth surface of more than 12 cm when combined with an increased rotation rate of more than 300 rpm as disclosed in WO 2019/138231. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® TurboDisk reactor.

Consequently, in a particularly preferred embodiment wherein the method of the present invention involves using a method as disclosed in WO 2017/029470, forming the porous monolayer of graphene on the growth surface by CVD comprises: providing the substrate on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; cooling the inlets to less than 100°C (i.e. so as to ensure that the precursor is cool as it enters the reaction chamber): introducing a carbon-containing precursor in a gas phase and/or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the substrate surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm.

The most common carbon-containing precursor in the art for graphene growth is methane (CI-14). Particularly preferred organic compounds for use as carbon-containing precursors are hydrocarbons, and methods of forming graphene therefrom by CVD, are described in GB 2604377, the contents of which is incorporated herein in its entirety.

The inventors have found that a porous monolayer of graphene may be formed directly on a substrate. A porous monolayer of graphene, as having been formed directly on the substrate, will be understood by those skilled in the art as referring generally to an incomplete layer of graphene whereby the surface coverage is less than 100%. That is, there will be gaps between crystals of graphene that leads voids or pores to expose the underlying substrate growth surface. The graphene layer may be considered "patchy".

In one extreme, the porous monolayer of graphene will be formed of a plurality (or an array) of individual and isolated graphene sheets (which may be referred to as graphene islands or flakes). Such islands are formed at nucleation points on the underlying crystalline substrate growth surface. Such nucleation points are generally randomly distributed, although certain techniques may enhance the provision of periodically spaced points. As growth of graphene continues and its surface coverage (as measured by area) increases, it will be appreciated that isolated islands may begin to coalesce to form larger islands of graphene. At higher surface coverage, the layer of graphene may be substantially continuous in that essentially all of the graphene is covalently connected (and therefore may be considered electrically connected). Generally, the surface coverage is at most 99% (by area) so as to have at least 1% open pores exposing the substrate growth surface so as to allow for nucleating the subsequent semiconductor layer growth. That is, the porous layer of graphene provides total graphene coverage of the growth surface of at most 99% and/or at least 50% (hence, the pores form 1 to 50% of the area of the growth surface. There is no specific lower limit, though is it preferred that the total coverage of the monolayer of graphene is at least 50%. Such a coverage may be that which provides an appreciable improvement in the quality of the subsequent semiconductor layer without restricting nucleation of the semiconductor layer growth such that the additional steps of graphene formation are worth the additional processing from a commercial perspective.

In some embodiments, it may be preferred for the graphene coverage to be at most 95%, or even at most 90% (i.e. the pores are 5 to 10% of the area). For example, from 50% to 90% may be preferred to provide a suitable range of coverage to reduce the strain in the semiconductor layer. In other embodiments, higher surface coverage may be preferred, for example at least 70%, or at least 90% and up to 99% so as to make the process of removing the semiconductor layer from the substrate easier due to the weak interactions with the intervening graphene layer facilitating lift-off as described herein.

The surface coverage may be readily ascertained by those skilled in the art using conventional imaging techniques such as atomic force microscopy (AFM).

The porous monolayer of graphene is an incomplete porous layer which will have pores randomly, but substantially homogeneously distributed across the whole layer. That is, the specific location of each pore is generally random, but the pore sizes and density are still constant across the growth surface. This can be determined through analysis of a number of representative regions of the graphene layer. For example, four regions of about 100 p.m2 evenly distributed across the graphene layer may be analysed to ensure surface coverage is substantially the same across the substrate and the porosity is evenly distributed. Those skilled in the art may readily reduce the size of the test area (to 10 km2 for example) and/or increase the number of regions to be analysed (to eight for example). As the surface coverage increases, smaller tests areas may be preferred to ensure even distribution of the reduced pore area.

Generally, an incomplete and therefore porous monolayer of graphene may be formed by halting the growth phase of a conventional growth process. For example, graphene formed by CVD may be made porous by reducing the time in which precursor is flowed into the CVD reaction chamber and, as described above, a skilled person may readily ascertain the porosity of the resulting layer. For example. "Structural properties of grain boundary in graphene grown on germanium substrates with different orientations" Wany et al., AppL Phys. Lett., 121,2022, 011901 discloses monitoring the consecutive growth and stitching process of graphene domains grown by CVD on Ge substrates, by AFM measurements.

There are numerous other parameters known to those skilled in the art associated with graphene growth, such as reaction chamber pressure, precursor and dilution gas flow rates and substrate growth temperature. Those skilled in the art may also readily adjust these parameters through routine experimentation to influence growth rates such that growth may be stopped before complete monolayer formation to afford a porous monolayer of graphene. The addition of hydrogen to the dilution gas may also assist in inducing hole formation in the graphene.

The method further comprises forming a semiconductor or dielectric layer on the growth surface of the substrate and the porous monolayer of graphene. The mechanism of growth of the semiconductor or dielectric layer is substantially equivalent to known ELO processes. The formation of the layer begins on the growth surface of the substrate through the pores of the monolayer of graphene. The may be formed by any suitable CVD/MOCVD processes.

Unlike the prior art, the process of forming porous graphene directly on the substrate can avoid contamination of the graphene layer and/or unintentional doping and formation of, for example, C-N dangling bonds. In particular, without wishing to be bound by theory, it is believed that the absence of organic polymer residues or remnants from plasma etching leaves a pristine surface upon which a higher quality semiconductor or dielectric layer with reduced strain and improved crystallinity may be grown. Moreover, by avoiding such processing, the growth surface of the substrate is not impacted which may otherwise occur during graphene etching. This can allow for the substrate to be reused many more times than known processes due to the absence of any risk in etching or damaging the growth surface. Additionally, the present method can prevent reformation of a native oxide on the exposed portions of the growth surface of the substrate which can occur using techniques based on masking and/or plasma etching, thereby maintaining a pristine growth surface for subsequent semiconductor layer growth.

In a particularly preferred embodiment, the steps of forming a porous monolayer of graphene and forming a semiconductor or dielectric layer are carried out sequentially in-situ in a CVD reaction chamber. That is, the porous graphene monolayer is therefore not exposed to the atmosphere between its formation and the formation of the semiconductor or dielectric layer ensuring a pristine graphene layer is retained.

Preferably, the semiconductor layer is formed of a Group II-VI or Group III-V semiconductor. In some embodiments, the semiconductor may comprise two or more of the materials described herein For example, in a first step, islands of semiconductor material such as AIN may be formed on the substrate in the pores of the graphene and, in a second step, a continuous layer of GaN may be formed thereon. The method may further comprises forming one or more further layers on the semiconductor layer, for example, one or more semiconductor layers. Such a process may be used to form a light-emitting or light-sensitive stack suitable for an LED or solar cell. Further layers may include a dielectric layer which may serve as a barrier layer between the semiconductor layer and a gate contact for a transistor.

When the layer is a dielectric layer, preferably the dielectric is a nitride or a fluoride. The dielectric layer is preferably formed from a material having a band gap of from 7 eV to 13 eV. Most preferable is the use of fluorides and nitrides of elements from groups 2, 3 and 13 of the periodic table. Examples include Sc, Y and La fluorides.

The method preferably comprises forming one or more electrical contacts suitable for connection to an electronic circuit. In this way, an array of devices may be formed across the substrate using conventional techniques such as photolithography. The substrate may be diced to afford individual devices. In alternative embodiments, the semiconductor layer and any further layers may be processed, for example by photolithography, and the substrate diced before one or more electrical contacts are formed on the individual processed laminates. Contacts are well known and are typically formed of metal, though other suitable contacts may also include transparent indium tin oxide (ITO).

As such, another aspect of the present invention provides a method of manufacturing an electronic device, the method comprising the steps of forming a semiconductor or dielectric layer on a substrate as described herein, and further comprising: forming one or more further layers on the semiconductor or dielectric layer; and forming one or more contacts for connection to an electronic circuit.

Either before or after forming further layers on the semiconductor layer, the method may also comprise separating the substrate from the semiconductor layer using the graphene as a separation layer. This may be a conventional lift-off process whereby the semiconductor layer may be transferred to another substrate and a device subsequently manufactured therefrom. Higher total coverages of graphene (e.g. from 70% to 99%, preferably from 90% to 99%), may facilitate the lift-off process. As a two dimensional material, graphene has only weak van der Waals interactions and minimal covalent interactions due to the retained pristine nature of the material by the process described herein. The weak interactions may be easily overcome so that the semiconductor layer is more easily removed.

During separation the graphene may remain at least partially on one or both of the substrate and the semiconductor or dielectric layer. The surface to which it remains adhered will depend on the nature of the materials making up each layer. Some further treatment may be desired to remove the graphene from one or both of these surfaces. This may permit reuse of the growth surface and/or use of the semiconductor layer as a future growth surface or a final surface of a final device. Suitable techniques are well known in the art for graphene removal and these may involve chemical treatments, sonication in an inert solvent, or treatments such as plasma or laser etching.

Preferably, the method further comprises repeating the steps of forming a porous monolayer of graphene and forming a semiconductor layer on the exposed growth surface of the substrate. That is, after removal of the graphene and semiconductor, the substrate may be reused in the process to manufacture further semiconductor layers for use in electronic devices. Preferably, the method further comprises a graphene removal step to remove the graphene which remains on either the substrate or semiconductor layer before either the substrate is reused in the process, or the semiconductor layer is transferred onto another desired substrate.

Figures The present invention will now be described further with reference to the following non-limiting Figure, in which: Figure 1 illustrates an exemplary method of manufacturing a semiconductor laminate according to the present invention.

Figure 1 illustrates an exemplary non-limiting method according to the present invention. Firstly, there is provided a substrate 100 formed of a silicon support and having an epitaxial AIN layer that provides the growth surface. An incomplete porous monolayer of graphene 105 is formed by CVD 200 directly on the AIN growth surface of the substrate 100. The porous monolayer of graphene 105 has pores 110 which expose portions of the underlying substrate 100. The total coverage of the graphene 105 on the substrate 100 as illustrated in Figure 1 is about 80%. Whilst the cross-section as illustrated in Figure 1 might suggest the presence of individual graphene islands (i.e. in essentially one dimension), the graphene 105 is substantially continuous across the substrate (i.e. in two dimensions) with essentially no isolated graphene islands.

In the same CVD chamber as that used for the CVD 200 of the porous graphene layer 105, growth of a semiconductor layer of GaN begins by MOCVD 205 using trimethylgallium and ammonia and Ga and N precursors, respectively, which results in the formation of GaN 115 initially in the pores of the graphene 105 on the exposed portion of the growth surface of the substrate 100. Growth by MOCVD continues 210 under the same conditions and the GaN continues to grow both vertically and laterally over the graphene 105 until coalescence and the formation of a complete continuous GaN layer 120.

Such as layer has significantly fewer defects and reduced strain over semiconductor layers formed by other known methods. The resulting semiconductor laminate is devoid of organic polymer as a result of such a material not being used in the manufacture the laminate.

Examples

A substrate was provided having a germanium growth surface. Graphene was grown on the germanium substrate according to the process in WO 2017/029470. Incomplete graphene having a porous configuration was grown by reducing the normal growth time required to ensure a complete layer. Coverage could be varied by adopting shorter or longer times. A GaN layer was then formed on the growth surface of the substrate and the porous monolayer of graphene. That is, the GaN grew through the pores of the graphene and a low defect density of the GaN was observed. After growth of the GaN layer, this was readily separated from the Germanium growth surface, using the graphene as a separation layer.

As used herein, the singular form of "a", "an" and "the" include plural references unless the context clearly dictates otherwise. The use of the term "comprising" is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to only those described. In other words, the term also includes the limitations of "consisting essentially of" (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and "consisting of" (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, layers and/or portions, the elements, layers and/or portions should not be limited by these terms. These terms are only used to distinguish one element, layer or portion from another, or a further, element, layer or portion. It will be understood that the term "on" is intended to mean "directly on" such that there are no intervening layers between one material being said to be "on" another material. Spatially relative terms, such as "under", "below", "beneath", "lower", "over". "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device as described herein is turned over, elements described as "under" or "below" other elements or features would then be oriented "over" or "above" the other elements or features. Thus, the example term "under" can encompass both an orientation of over and under. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents.

Claims

Claims: 1. A method of forming a semiconductor or dielectric layer on a substrate, the method comprising: providing a substrate having a growth surface; forming a porous layer of graphene, preferably a porous monolayer of graphene, on the growth surface of the substrate; and forming a semiconductor or dielectric layer on the growth surface of the substrate and the porous layer of graphene.
2. The method according to claim 1, wherein the porous layer of graphene is formed on the growth surface of the substrate by CVD.
3. The method according to claim 2, wherein the steps of forming a porous layer of graphene and forming a semiconductor or dielectric layer are carried out sequentially in-situ in a CVD reaction chamber.
4. The method according to any one of the preceding claims, wherein the semiconductor layer is formed of a Group II-VI or Group III-V semiconductor.
5. The method according to any one of the preceding claims, wherein the growth surface of the substrate is formed of a Group IV or Group II-VI or Group III-V material, preferably a Group IV or Group II-VI or Group III-V semiconductor.
6. The method according to claim 4 or claim 5, wherein the group III element of the Group III-V material and/or Group III-V semiconductor is selected from one or more of the group consisting of B, Al. Ga and In, and the group V element is selected from or more of the group consisting of N. P, As and Sb.
7. The method according to claim 5, wherein the group IV element is selected from one or more of the group consisting of C, Si and Ge.
8. The method according to claim 7. wherein the growth surface of the substrate is formed of Ge.
9. The method according to any one of the preceding claims, wherein the semiconductor or dielectric layer is formed of the same material which forms the growth surface of the substrate.
10. The method according to any one of the preceding claims, wherein the porous layer of graphene provides total graphene coverage of the growth surface of at most 99% and/or at least 50%.
11. The method according to any one of the preceding claims, further comprising separating the substrate from the semiconductor or dielectric layer, whereby the porous layer of graphene remains at least partially on one or both of the substrate and the semiconductor or dielectric layer.
12. The method according to claim 11, further comprising repeating the steps of forming a porous layer of graphene and forming a semiconductor or dielectric layer on the exposed growth surface of the substrate.
13. A laminate obtainable by the method of any one claims 1 to 10.
14. A laminate comprising: a substrate; a porous layer of graphene, preferably a porous monolayer of graphene, on a surface of the substrate; and a semiconductor or dielectric layer on the surface of the substrate and the porous layer of graphene; wherein the laminate is devoid of organic polymer.
15. An electronic device comprising the laminate of claim 13 or claim 14, preferably an opto-electronic device or transistor.
16. A method of manufacturing an electronic device of claim 15, the method comprising the method of any one of claims 1 to 10 and further comprising: forming one or more further layers on the semiconductor or dielectric layer; and forming one or more contacts for connection to an electronic circuit.