GB2617506A - Sigma-delta modulator with residue converter for low-offset measurement system - Google Patents
Sigma-delta modulator with residue converter for low-offset measurement system Download PDFInfo
- Publication number
- GB2617506A GB2617506A GB2310553.9A GB202310553A GB2617506A GB 2617506 A GB2617506 A GB 2617506A GB 202310553 A GB202310553 A GB 202310553A GB 2617506 A GB2617506 A GB 2617506A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- modulator
- processing system
- output signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims 15
- 230000003044 adaptive effect Effects 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 claims 2
- 238000006731 degradation reaction Methods 0.000 claims 2
- 230000004044 response Effects 0.000 claims 2
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/352—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M3/354—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M3/356—Offset or drift compensation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
- H03M3/416—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type all these quantisers being multiple bit quantisers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.
Claims (30)
1. A signal processing system comprising: a sensor readout channel configured to convert an electronic signal into a digital quantity, the sensor readout channel comprising: a first-order sigma-delta modulator having a modulator input and a modulator output; first outside chopping switches located at the modulator input; second outside chopping switches located at the modulator output; an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator; and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.
2. The signal processing system of Claim 1, wherein the memory element comprises an integrator.
3. The signal processing system of Claim 1 or 2, further comprising an impedance for converting a sensed physical quantity into the electronic signal.
4. The signal processing system of Claim 3, wherein: the electronic signal is a voltage; and the impedance is a resistor configured to convert an electrical current into the voltage.
5. The signal processing system of Claim 4, wherein the sensor readout channel further comprises a digital accumulator configured to digitally integrate the combined output signal to generate the digital quantity representing a net amount of charge that has flowed through the impedance.
6. The signal processing system of Claim 4 or 5, wherein the digital quantity represents a net amount of charge that has been delivered from a battery coupled to the impedance.
7. The signal processing system of any preceding Claim, wherein the sensor readout channel further comprises a digital accumulator configured to digitally integrate the combined output signal to generate an accumulated combined output signal.
8. The signal processing system of any of Claims 1-6, wherein the sensor readout channel further comprises a digital accumulator configured to digitally integrate the modulator output signal to generate an accumulated modulator output signal, and the combiner is configured to combine the accumulated modulator output signal with the auxiliary path output signal to generate the combined output signal.
9. The signal processing system of any preceding Claim, further comprising an anti-aliasing filter coupled between an input for receiving the electronic signal and the modulator input.
10. The signal processing system of Claim 9, wherein the anti-aliasing filter is located in a path of the sensor readout channel between the first outside chopping switches and the second outside chopping switches.
11. The signal processing system of Claim 9 or 10, wherein the first outside chopping switches are located in a path of the sensor readout channel between the input for receiving the electronic signal and the anti-aliasing filter.
12. The signal processing system of any preceding Claim, further comprising an adaptive gain element applied to the auxiliary path output in order to minimize signal- to-noise degradation due to non-idealities of analog components of the signal processing system.
13. The signal processing system of any preceding Claim, wherein the sigma- delta modulator comprises a 3-level quantizer.
14. The signal processing system of Claim 13, wherein the 3-level quantizer is configured to, during production test of the signal processing system, detect the combined output signal in response to a pilot signal injected into an input of the signal processing system to determine a threshold mismatch of the 3-level quantizer.
15. The signal processing system of any preceding Claim, wherein the auxiliary signal path is configured such that it is only enabled upon a readout request for the combined output signal.
16. A method comprising, in a system comprising a sensor readout channel configured to convert an electronic signal into a digital quantity, the sensor readout channel comprising a first-order sigma-delta modulator having a modulator input and a modulator output: switching first outside chopping switches located at the modulator input and second outside chopping switches located at the modulator output in synchronization; receiving, by an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, as its input signal a signal output by a memory element of the first-order sigma-delta modulator; and combining a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.
17. The method of Claim 16, wherein the memory element comprises an integrator.
18. The method of Claim 16 or 17, further comprising converting a sensed physical quantity into the electronic signal with an impedance.
19. The method of Claim 18, wherein: the electronic signal is a voltage; and the impedance is a resistor configured to convert an electrical current into the voltage.
20. The method of Claim 19, further comprising digitally integrating, with a digital accumulator integral to the sensor readout channel, the combined output signal to generate the digital quantity representing a net amount of charge that has flowed through the impedance.
21. The method of Claim 19 or 20, wherein the digital quantity represents a net amount of charge that has been delivered from a battery coupled to the impedance.
22. The method of any of Claims 16-21, further comprising digitally integrating, with a digital accumulator integral to the sensor readout channel, the combined output signal to generate an accumulated combined output signal .
23. The method of any of Claims 16-21, further comprising: digitally integrating, with a digital accumulator integral to the sensor readout channel, the modulator output signal to generate an accumulated modulator output signal; and combining the accumulated modulator output signal with the auxiliary path output signal to generate the combined output signal.
24. The method of any of Claims 16-23, further comprising an anti-aliasing filter coupled between an input for receiving the electronic signal and the modulator input .
25. The method of Claim 24, wherein the anti-aliasing filter is located in a path of the sensor readout channel between the first outside chopping switches and the second outside chopping switches.
26. The method of Claim 24 or 25, wherein the first outside chopping switches are located in a path of the sensor readout channel between the input for receiving the electronic signal and the anti-aliasing filter.
27. The method of any of Claims 16-26, further comprising applying an adaptive gain element to the auxiliary path output in order to minimize signal-to-noise degradation due to non-idealities of analog components of the signal processing system.
28. The method of any of Claims 16-27, wherein the sigma-delta modulator comprises a 3 -level quantizer.
29. The method of Claim 28, further comprising, during production test of the signal processing system, detecting the combined output signal in response to a pilot signal injected into an input of the signal processing system to determine a threshold mismatch of the 3 -level quantizer.
30. The method of any of Claims 16-29, enabling the auxiliary signal path only upon a readout request for the combined output signal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163148832P | 2021-02-12 | 2021-02-12 | |
| US17/232,949 US20220263520A1 (en) | 2021-02-12 | 2021-04-16 | System-level chopping in coulomb counter circuit |
| PCT/US2022/015827 WO2022173835A1 (en) | 2021-02-12 | 2022-02-09 | Sigma-delta modulator with residue converter for low-offset measurement system |
| US17/667,953 US11777516B2 (en) | 2021-02-12 | 2022-02-09 | Sigma-delta modulator with residue converter for low-offset measurement system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2617506A true GB2617506A (en) | 2023-10-11 |
Family
ID=80628909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB2310553.9A Pending GB2617506A (en) | 2021-02-12 | 2022-02-09 | Sigma-delta modulator with residue converter for low-offset measurement system |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR20230144076A (en) |
| GB (1) | GB2617506A (en) |
| WO (1) | WO2022173835A1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1705493B1 (en) * | 2005-03-22 | 2008-11-12 | Telefonaktiebolaget LM Ericsson (publ) | A method and device for battery capacity calculation using shift of measurement range |
| US20110063146A1 (en) * | 2009-09-15 | 2011-03-17 | Texas Instruments Incorporated | Multistage chopper stabilized delta-sigma adc with reduced offset |
| US9438261B2 (en) * | 2014-04-09 | 2016-09-06 | Ams Ag | Capacitance-to-digital converter and method for providing a digital output signal |
-
2022
- 2022-02-09 WO PCT/US2022/015827 patent/WO2022173835A1/en active Application Filing
- 2022-02-09 KR KR1020237031025A patent/KR20230144076A/en unknown
- 2022-02-09 GB GB2310553.9A patent/GB2617506A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1705493B1 (en) * | 2005-03-22 | 2008-11-12 | Telefonaktiebolaget LM Ericsson (publ) | A method and device for battery capacity calculation using shift of measurement range |
| US20110063146A1 (en) * | 2009-09-15 | 2011-03-17 | Texas Instruments Incorporated | Multistage chopper stabilized delta-sigma adc with reduced offset |
| US9438261B2 (en) * | 2014-04-09 | 2016-09-06 | Ams Ag | Capacitance-to-digital converter and method for providing a digital output signal |
Non-Patent Citations (1)
| Title |
|---|
| FRAISSE CHRISTIAN ET AL, "A [Sigma][Delta] sense chain using chopped integrators for ultra-low-noise MEMS system", ESSCIRC CONFERENCE 2016: 42ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, IEEE, (20160912), pgs 153-156, DOI:10.1109/ESSCIRC.2016.7598265, figs 1-3, pg 153, left-hand col, line 1 - pg 155 * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20230144076A (en) | 2023-10-13 |
| WO2022173835A1 (en) | 2022-08-18 |
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