GB2601900B - Coherency manager - Google Patents

Coherency manager Download PDF

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Publication number
GB2601900B
GB2601900B GB2115397.8A GB202115397A GB2601900B GB 2601900 B GB2601900 B GB 2601900B GB 202115397 A GB202115397 A GB 202115397A GB 2601900 B GB2601900 B GB 2601900B
Authority
GB
United Kingdom
Prior art keywords
coherency manager
coherency
manager
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2115397.8A
Other versions
GB202115397D0 (en
GB2601900A (en
Inventor
John Robinson Martin
Landers Mark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imagination Technologies Ltd
Original Assignee
Imagination Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imagination Technologies Ltd filed Critical Imagination Technologies Ltd
Priority to GB2115397.8A priority Critical patent/GB2601900B/en
Priority claimed from GB2019595.4A external-priority patent/GB2589022B/en
Publication of GB202115397D0 publication Critical patent/GB202115397D0/en
Publication of GB2601900A publication Critical patent/GB2601900A/en
Application granted granted Critical
Publication of GB2601900B publication Critical patent/GB2601900B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB2115397.8A 2018-02-28 2018-02-28 Coherency manager Active GB2601900B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2115397.8A GB2601900B (en) 2018-02-28 2018-02-28 Coherency manager

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB2019595.4A GB2589022B (en) 2018-02-28 2018-02-28 Coherency manager
GB2115397.8A GB2601900B (en) 2018-02-28 2018-02-28 Coherency manager

Publications (3)

Publication Number Publication Date
GB202115397D0 GB202115397D0 (en) 2021-12-08
GB2601900A GB2601900A (en) 2022-06-15
GB2601900B true GB2601900B (en) 2022-11-16

Family

ID=81656137

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2115397.8A Active GB2601900B (en) 2018-02-28 2018-02-28 Coherency manager

Country Status (1)

Country Link
GB (1) GB2601900B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825412A (en) * 1988-04-01 1989-04-25 Digital Equipment Corporation Lockout registers
US5257361A (en) * 1989-10-30 1993-10-26 Hitachi, Ltd. Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4825412A (en) * 1988-04-01 1989-04-25 Digital Equipment Corporation Lockout registers
US5257361A (en) * 1989-10-30 1993-10-26 Hitachi, Ltd. Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation

Also Published As

Publication number Publication date
GB202115397D0 (en) 2021-12-08
GB2601900A (en) 2022-06-15

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