GB2589022B - Coherency manager - Google Patents
Coherency manager Download PDFInfo
- Publication number
- GB2589022B GB2589022B GB2019595.4A GB202019595A GB2589022B GB 2589022 B GB2589022 B GB 2589022B GB 202019595 A GB202019595 A GB 202019595A GB 2589022 B GB2589022 B GB 2589022B
- Authority
- GB
- United Kingdom
- Prior art keywords
- coherency manager
- coherency
- manager
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
- G06F12/1018—Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2115397.8A GB2601900B (en) | 2018-02-28 | 2018-02-28 | Coherency manager |
GB2019595.4A GB2589022B (en) | 2018-02-28 | 2018-02-28 | Coherency manager |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2001366.0A GB2579921B (en) | 2018-02-28 | 2018-02-28 | Coherency manager |
GB2019595.4A GB2589022B (en) | 2018-02-28 | 2018-02-28 | Coherency manager |
Publications (3)
Publication Number | Publication Date |
---|---|
GB202019595D0 GB202019595D0 (en) | 2021-01-27 |
GB2589022A GB2589022A (en) | 2021-05-19 |
GB2589022B true GB2589022B (en) | 2021-12-15 |
Family
ID=74189115
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2019595.4A Active GB2589022B (en) | 2018-02-28 | 2018-02-28 | Coherency manager |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2589022B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4825412A (en) * | 1988-04-01 | 1989-04-25 | Digital Equipment Corporation | Lockout registers |
US5257361A (en) * | 1989-10-30 | 1993-10-26 | Hitachi, Ltd. | Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation |
-
2018
- 2018-02-28 GB GB2019595.4A patent/GB2589022B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4825412A (en) * | 1988-04-01 | 1989-04-25 | Digital Equipment Corporation | Lockout registers |
US5257361A (en) * | 1989-10-30 | 1993-10-26 | Hitachi, Ltd. | Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation |
Also Published As
Publication number | Publication date |
---|---|
GB2589022A (en) | 2021-05-19 |
GB202019595D0 (en) | 2021-01-27 |
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