GB2596295A - Power semiconductor device with segmented MESA trenches - Google Patents

Power semiconductor device with segmented MESA trenches Download PDF

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Publication number
GB2596295A
GB2596295A GB2009511.3A GB202009511A GB2596295A GB 2596295 A GB2596295 A GB 2596295A GB 202009511 A GB202009511 A GB 202009511A GB 2596295 A GB2596295 A GB 2596295A
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United Kingdom
Prior art keywords
semiconductor region
trench
mesa
semiconductor
dimension
Prior art date
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Withdrawn
Application number
GB2009511.3A
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GB202009511D0 (en
Inventor
Udrea Florin
Pathirana Vasantha
Wa Chan Chun
Trajkovic Tanya
Udugampola Nishad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd
Global Energy Interconnection Research Institute
Global Energy Interconnection Res Institute Europe GmbH
Original Assignee
Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd
Global Energy Interconnection Research Institute
Global Energy Interconnection Res Institute Europe GmbH
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Application filed by Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd, Global Energy Interconnection Research Institute, Global Energy Interconnection Res Institute Europe GmbH filed Critical Electric Power Research Institute of State Grid Shandong Electric Power Co Ltd
Priority to GB2009511.3A priority Critical patent/GB2596295A/en
Publication of GB202009511D0 publication Critical patent/GB202009511D0/en
Publication of GB2596295A publication Critical patent/GB2596295A/en
Withdrawn legal-status Critical Current

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

Abstract

The device comprises second conductivity type 6 and first conductivity type 7 regions having higher doping concentrations than a first conductivity channel body 5 located on the channel body and contacting an emitter electrode; active trenches 20 adjoining the emitter region extending from the surface through the channel body region into the drift region in a first dimension; segmented mesa trenches 30 placed between two active gate trenches in a second dimension and extending from the surface through the channel body into the drift region, where the mesa trenches are segmented in a third dimension and one first conductivity type contact region is placed between the spacing of two segmented mesa trenches in the third dimension, and the second conductivity type contact region extends from one of the mesa trenches to an active trench in the second dimension and a highly conductive layer of the active trenches is connected electrically to a common gate electrode, and the highly conductive layer of the mesa trench is connected electrically to either the gate electrode, the emitter electrode or left floating.

Description

POWER SEMICONDUTOR DEVICE WITH SEGEMENTED MESA TRENCHES
Field of the Disclosure
The present invention relates to a vertical insulated gate bipolar transistor in trench technology featuring segmented mesa trenches between two active gate trenches around the emitter region.
Background of the Disclosure
Insulated Gate Bipolar Transistors (IGBTs) play a central role in various high-voltage power switching applications such as motor control, inverter and switched mode power supply, owing to their relatively low on-state voltage drop (VON) arising from conductivity modulation and ability to drive the device easily via the insulated gate. With the application of trench technology, IGBTs became an even more attractive device of choice due to higher channel density, no parasitic JFET and stronger injection enhancement (1E) effect. The IE effect is crucial to the improvement of trade-off between the turn-off loses, EOFF vs. VON losses of the IGBTs.
Fig. 1 depicts a prior art trench IGBT design comprising a collector p+ layer 1, a N field stop layer 2 and an N drift layer 3. In this figure narrower mesa width 'L (in a second dimension) is desired as it impedes the hole collection by the emitter 10 while increasing locally the electron current density thereby enhancing IE effect. Another solution to enhance the IE effect was to add a carrier storage layer nwell 4 below the pwell region 5 with as high doping as possible. However, if the doping of the nwell 4 is too high, the breakdown of the device can be negatively affected. To prevent the breakdown degradation associated with increased nwell 4 doping, the mesa width 1' must be reduced accordingly. In addition to background degradation due to avalanche around the corner of the trenches, punch-trough breakdown can also occur when the p body 5 is too thin or too lowly doped. The punch-through effect is also enhanced at high temperatures. Finally a large L could also result in reliability effects associated with the insulated gate 22 in the trenches 20. Such effects could be tunneling through the insulating gate 21, or hot carrier injection effects or time dependent dielectric breakdown.
Even though narrow mesa width L' is desirable for IE effect, the mesa region must be kept sufficiently wide to allow formation of good Ohmic contacts to both emitter n+ and p+ regions 6, 7. Poor Ohmic contacts will lead to performance deteriorations such as increased contact resistance, decreased latch-up current and instability of threshold voltage and saturation current. This limits the maximum possible nwell 4 doping and therefore hinders further improvement of the trade-off Alternatively, placing the emitter n+ and p+ regions 6, 7 in the third dimension on the surface of pwell 5 as shown in Fig. 2 can help to form a good Ohmic contact with narrower mesa width, but further shrinking of the mesa distance is desirable. Furthermore compared to Fig. 1, in Fig. 2 the emitter p+ contact 7 is at the surface and not below emitter n+ 6. This may hinder the devices immunity to latch-up as more hole current will now have to travel under the emitter n+ One solution to this problem, is a trench IGBT structure with the bottom of the gate trench expanded symmetrically to create a Partially Narrow Mesa structure. A narrower gap at the bottom of the gate trenches helps to increase the nwell doping there by achieving stronger IF effect. However, this approach requires special processing. Another solution that has been proposed is a trench IGBT designed with a p-type region at the trench bottom. The 'p-ring' layer under the gate trench compensates for the increase in the nwell doping through a local RESURF effect, so that higher doping can be used in the nwell to boost the IF effect while supporting the breakdown. However, this approach also requires fine tuning of the process to keep the layers at the desired location while achieving local RESURF effect Fig. 3 depicts an insulated gate bipolar device with the presence of one or more segmented trenches 30 in the mesa region comprising an insulating layer 31 and a conductive material 32, arranged between island-like pwell regions 5 in the third dimension. This design may reduce Miller capacitance and improve the IE effect compared to previous design, However, because of the absence of the pwell where mesa trench is present trenches have to be very close to support high breakdown with high nwell doping.
Fig. 4 shows an insulated gate bipolar device using a recessed emitter trench 60 between two active trenches 20. The structure of recessed emitter trench 60 is similar to that of segmented trenches 30 shown in Fig. 3. The emitter trench 60 has 3D features including "S" shape and segmentation in the extending direction of the active trench 20. During operation the recessed emitter trench 60 allows miniaturised trench-to-trench spacing to be achieved without photolithographic limitations. This allows the doping of the nwell layer 4 to be increased without degrading the breakdown voltage. This design also requires a special processing platform.
In the prior art described above the IE effect is important in achieving low loss, high-efficiency trench IGBT. Therefore, the designs demonstrate ways to enhance the IE effects, including the reduction of mesa width I' and increase of carrier storage layer doping. The latter method usually comes with mesa distance narrowing to support the breakdown voltage. To keep manufacturability of IGBT products, the extent to which the trench-to-trench distance can be reduced is limited by the photolithographic limitations on forming good n+ and p+ emitter contacts 6,7 in the mesa region. Emitter contact area is required to be wide enough to prevent large contact resistances, poor SOA performance, low yield and reliability issues.
Summary
The present invention is defined by the independent claims. Preferred embodiments are defined in the dependent claims.
We herein describe a bipolar semiconductor transistor having a high voltage terminal (collector) or first terminal, a low voltage terminal (emitter) or second terminal and a control terminal (gate), the bipolar semiconductor transistor comprising: a collector region or a first semiconductor region of a first conductivity type connected to the collector terminal; a drift region or a second semiconductor region of a second conductivity type located over the collector region; an optional field stop layer of second conductivity type which has higher doping than the drift region, sandwiched between first and second semiconductor layers; a carrier storage region or the third semiconductor region of a second conductivity type having higher doping than the drift region, formed over the drift region; a channel body region or the fourth semiconductor of a first conductivity type located over the carrier storage region; a plurality of second conductivity type and first conductivity type contact regions having higher doping concentrations than the channel body region located on the surface of the channel body region and in direct contact with the emitter terminal; at least two active trenches adjoining the second conductivity emitter region extending from the surface, through the channel body region into the drift region in a first dimension; at least two segmented mesa trenches, placed between two active gate trenches in a second dimension and extending from the surface, through the channel body region into the drift region, wherein the mesa trenches are segmented in a third dimension and wherein at least one first conductivity type contact region is placed between the spacing of the at least two segmented mesa trenches in the third dimension, and wherein the second conductivity type contact region extends from at least one of the mesa trench to an active trench in the second dimension; and wherein all trenches comprise an insulated layer and a highly conductive layer, in contact with the insulated layer, and wherein the highly conductive layer of the active trenches is connected electrically to the gate terminal, and wherein the highly conductive layer of the at least one mesa trench is connected electrically to either the gate terminal, the emitter terminal or not connected to a terminal and, wherein, in the on-state operation, a channel of carriers of second conductivity type is formed along each active trench and within the channel body region, and wherein the drift region is conductivity modulated by the second conductivity carriers injected from the carriers storage region and the first conductivity carriers injected from the collector region.
It will be understood that the second dimension is generally a X-axis or horizontal axis, the first dimension is generally a Y-axis or vertical axis (or the direction of current) and the third dimension is generally the Z-axis which is neither the horizontal nor vertical axis but extends towards the depth of the device (as opposed to length and width of the device).
Optionally, the at least two mesa trench may be configured to increase the doping concentration of the carrier storage layer, to improve the on-state performance of the semiconductor device without a significant penalty in breakdown, reliability or turn-off losses The highly conductive layer inside at least one segmented mesa trench may be connected to the emitter terminal, the gate terminal, or may be floating (i.e. not connected to any terminal).
Optionally, the gap between at least one segment of the mesa trench and the active trench may be sufficiently small in the second dimension so that the mesa trench and the active trench act together to push the depletion region deeper into the first dimension, away from the bottom of the trenches and therefore allowing an increase the carrier storage charge layer doping, without significantly compromising the breakdown or the turn-off losses.
Additionally or alternatively, the gap between the at least two segments of the mesa trenches placed between the active trenches in the second dimension is sufficiently small so that the at least two mesa trenches act together act together to push the depletion region deeper into the first dimension, away from the bottom of the trenches and therefore allowing an increase the carrier storage charge layer doping, without significantly compromising the breakdown or the turnoff losses. During this action, the carrier storage layer is laterally depleted in the second dimension by the action of the depletion region around the active and mesa trenches.
The emitter contact to the emitter terminal may be formed only within the gap between the segmented mesa trenches in the third dimension In some embodiments, additional dummy trenches may be placed in the second dimension adjacent to active trenches and where the additional dummy trenches have the highly conductive layer inside them connected to the emitter terminal. Additionally or alternatively, the highly conductive layer of the dummy trenches may be connected to the gate control terminal or may be floating (i.e. not connected to any terminal).
Optionally, the semiconductor device may be an Insulated Gate Bipolar Transistor (IGBT).
Optionally, the collector region may contain at least one region of the second conductivity type connected to the collector terminal thereby forming a Reverse Conducting Insulated Gate Bipolar Transistor
Brief Description of Drawings
Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which: FIG.1 is a semiconductor device according to the prior art, wherein emitter p+ contact is formed in a shallow recessed region extending in parallel with the gate trench; FIG.2 is a semiconductor device according to the prior art, wherein emitter p+ and n+ contacts form an alternate pattern in the extending direction of the gate trench. This structure can be used to narrow the mesa region; FIG.3 is a semiconductor device according to the prior art, where there is a segmented mesa trench between active trenches and channel is formed in between the segments. This structure will allow higher doping for the CSL layer; FIG.4 is a semiconductor device according to the prior art, where there is a recessed mesa trench between active trenches connected to the emitter. This structure will allow higher doping for the CSL layer; FIG.5 shows a semiconductor device according to this invention, wherein mesa trench is placed between two gate trenches and the mesa trench is segmented. The space between the segments accommodates recessed emitter p+ contact. In this structure mesa trench is connected to the emitter terminal; FIG.6 depicts the breakdown curves for prior art structure in Fig 1 compared against the current invention and it shows CSL layer doping can be increased in the current invention without degrading the breakdown voltage; FIG.7 shows the on-state I-V curves, for the structures in Fig.1 and Fig.5. It is shown that VON is lower in the embodiment according to current invention; FIG.8 shows the EOFF vs. VON trade-off plot, for the structures in Fig.1 and Fig.5. It is shown that better trade-off can be achieved with the structure in the current invention; FIG.9 is a semiconductor device according to the current invention where two mesa trenches are inserted between the active trenches to allow even higher CSL doping; FIG.10 is a semiconductor device according to the current invention where mesa trench is connected to the gate terminal; FIG.11 is a semiconductor device according to the current invention where mesa trench is at floating potential; FIG.12 is a semiconductor device according to the current invention where emitter contact is place within the space between the mesa trenches in the 3d dimension; and FIG.13 is a semiconductor device according to the current invention where cell pitch is increased by adding dummy trenches between two active trenches away from the emitter region. This figure shows dummy trenches being segmented into portions and space between the segments accommodating p+ recessed contact region connecting the pwell regions between the dummy trenches to emitter potential.
FIG.14 is a semiconductor device according to the current invention where it is applied to a Reverse Conducting IGBT (RC-IGBT)
Detailed Description of the Preferred Embodiments
We note that several features shown in the following features correspond to features show in Figs. 1-4, and the same reference numerals are used for these features.
Fig. 5 shows a trench IGBT using a substrate made up of a n-type drift region 3 over a n-type field stop layer 2. Underneath this layer 2, a p-type region 1 is formed and connected to the collector terminal. On the opposite side of the substrate, a pwell layer 5 (the channel body region) is positioned on top of a n-type carrier storage layer nwell 4. The active gate trench 20 extends from the surface into the drift region in a first dimension. The mesa trench 30 is formed between two active trenches 20 (with the conductive material 32-preferably made of polysilicon-contacted to gate) in a second dimension and is segmented in the third dimension. Emitter p+ contact 7 resides between the mesa trenches where there is a gap between the segments. The presence of the mesa trench allows higher doping concentration of the nwell (CSL) layer 4, which improves the on-state performance without a penalty in the punch-through or avalanche breakdowns, or reliability effects, or significantly higher turn-off losses. The concentration of the nwell should be in excess of about 1.10'acm-3 and ideally above about 1 1016cm-3 to act as a strong electron injector during on-state. It is however important that the nwell 4 depletes during the blocking mode in the off-state and therefore the distance between the active trenches 20 and the mesa trench 30 should be smaller than about 2 micrometers and ideally smaller than about 1 micrometer. This would allow the depletion regions around the active trench 20 and the mesa trench 30 in the first direction to join and deplete the n well laterally in the second dimension.
The emitter n+ layer 6 is positioned between mesa trench 30 and active gate trench 20. The distance between mesa trenches W', in the third dimension, may be as small as possible while still allowing enough room to form a good p+ contact, 7. In this embodiment emitter contact 10 connects n+ 6, p+ 7 and mesa trench 30 to the emitter potential. The mesa trench 30 may help to push the depletion region and the potential deeper into the substrate and hence relax the electric field around the trench bottom. This will allow higher doping to be used for the nwell layer 4 (CSL) to facilitate injection enhancement without degrading the breakdown voltage (see Fig. 6). Furthermore the presence of the mesa trench 30 reduces reliability effects associated with the high electric field at the bottom of the trench such as hot carrier degradation or time dependent dielectric breakdown. The benefit of the high doping in the n-well 4 (CSL) layer to the on-state performance is depicted in Fig. 7.
Figs. 6 and 7 show a comparison of the breakdown voltages and the on-state performance respectively of embodiments of the present invention in comparison to that of prior art designs.
Fig. 8 shows the EOFF vs. VON trade-off relationship between the prior art (e.g. as shown in Fig. 1) and embodiments of the current invention. When connected to the emitter electrode, the mesa trench 30 will also help to lower the gate to drain capacitance by associating more of the gate capacitance with the emitter 10. A reduced Millar capacitance may help to lower the switching losses. Tests of the present invention have shown that embodiments with a high nwell 4 (CSL) doping show the best trade-off. As this design allows more area for the emitter p+ contact 7, the p+ 7 can be made deeper On the first dimension) than the emitter n+ 6 using a shallow trench and this will improve the devices immunity to latch-up thereby improving the safe operating area (SCA).
Fig. 9 shows an IGBT with two mesa segmented trenches 30 between the two gate trenches 20. The skilled person will understand that the use of two mesa segmented trenches is merely an example, and that any number of mesa segmented trenches 30 may be added between the gate trenches 20. The advantage of this structure is that the distance between the trenches can be further narrowed allowing higher nwell 4 doping to be used without affecting the breakdown voltage. The concentration of the nwell 4 should be in excess of about 1 10I6cm-3 and ideally above about 1 1015cm-3 to act as a strong electron injector during on-state. It is however important that the nwell 4 depletes during the blocking mode in the off-state and therefore the distance between the active trenches 20 and the mesa trench 30 should be smaller than about 2 micrometers and ideally smaller than about 1 micrometer. The distance between the two mesa segmented trenches 30 in the second dimension should also be smaller than about 2 micrometers and ideally smaller than about 1 micrometer.
In Figs. 5 and 9, the mesa trench(es) 30 are connected to the emitter 10. However, it is possible to have the mesa trench 30 (e.g. the conductive layer 32 inside the mesa trench) connected to the gate 22 or floating. This may be necessary to control switching parameters such as dl/dt, dv/dt and voltage spikes in some applications.
Fig. 10 shows an example of a trench IGBT according to the present invention with mesa trench 30 connected to the gate 22.
Fig. 11 shows an example of a trench IGBT according to the present invention with a floating mesa trench 30. As can be seen in this figure, mesa trench 30 is not connected to emitter contact 10.
In Fig. 12 the emitter contact 10 is placed within the space between mesa trenches 30. In this way the distance between the trenches 20 can be further reduced provided there is enough of a gap between the mesa trenches 30 to form both the n+ and p+ contacts 6 and 7.
Even though the structures in Fig. 5 and Figs. 10-12 showed a cell with just the mesa region, the cell width can be extended as shown in Fig. 13 to lower the saturation current and improve the short circuit safe operating area (SCSOA). In this figure, dummy region 100 is the extended area and trenches 50 in this region are connected to the emitter electrode via contacts 10. However, alternatively trenches 50 may be connected to gate 22 or left floating. The pwell regions 7 between the dummy trenches 50 are connected to the emitter and the gap between the segmented dummy trenches are used to form the emitter contact. It should be noted that pwell regions 7 between the dummy trenches in the dummy region can also be left floating.
While embodiments described above are based on a standard IGBT, the invention may also be implemented with a Reverse Conduction IGBTs (RC-IGBTs) as in Fig. 14. An RC IGBT is based on an IGBT structure with an additional n+ layer 200 placed inside the collector region and connected to the collector terminal. The n+ region 200 serves as the cathode of an anti-parallel diode, which conducts current during the reverse conduction mode. In Fig. 14 the n+ layer 200 is shown placed in the third dimension, but it will be appreciated that it may be placed in the second dimension.
It should be understood that the embodiments listed above are not exhaustive and that features from one embodiment may be combined with those of other embodiments.
References 1. M. Sumitomo et al., "Low loss IGBT with Partially Narrow Mesa Structure (PNM-IGBT)", Proceedings of 24th ISPSD, 2012, pp. 17-20 2. M. Antoniou et al., "Novel Approach Toward Plasma Enhancement in Trench-Insulated Gate Bipolar Transistors", IEEE Electron Device Letters, 2015, Vol. 36, No. 8 3. Y. Onozawa et al., "Semiconductor Device", Patent No. US 9,099,522 B2, Aug. 2015 4. I. Deviny et al., "A Semiconductor Device", Patent No. WO 2018/215727 Al, Nov 2018 5. Y. Yao et al., "A 750V Recessed-Emitter-Trench IGBT with Recessed-Dummy-Trench Structure Featuring Low Switching Losses", Proceedings of 30th ISPSD, 2018, pp. 112-115

Claims (16)

  1. CLAI MS: 1 A bipolar semiconductor transistor comprising a first terminal, a second terminal and a control terminal, and further comprising: a first semiconductor region operatively connected to the first terminal, wherein the first semiconductor region is of a first conductivity type; a second semiconductor region located over the first semiconductor region, wherein the second semiconductor region is of a second conductivity type; a third semiconductor region located over the second semiconductor region, wherein the third semiconductor region is of the second conductivity type, and wherein a doping concentration of the third semiconductor region is greater than a doping concentration of the second semiconductor region; a fourth semiconductor region located over the third semiconductor region, the fourth semiconductor region of the first conductivity type; at least two active trench regions extending from the fourth semiconductor region to the second semiconductor region in a first dimension, wherein the at least two active trench regions comprise an insulated layer and a conductive layer, and wherein the conductive layer is operatively connected to the control terminal; at least one mesa trench formed between and separated from the at least two active trench regions in a second dimension and extending from the fourth semiconductor region to the second semiconductor region in the first dimension, wherein the at least one mesa trench comprises a plurality of discrete mesa trench regions separated in a third dimension, and wherein the at least one mesa trench comprises an insulated layer and a conductive layer, the conductive layer operatively connected to the control terminal; a plurality of contact regions formed over the fourth semiconductor region and operatively connected to the second terminal, wherein the plurality of contact regions comprises: at least one contact region of the first conductivity type formed between the plurality of discrete mesa trench regions in the third dimension; and at least one contact region of the second conductivity type formed between the at least one mesa trench and the at least two active gate regions; wherein a doping concentration of each of the plurality of contact regions is greater than a doping concentration of the fourth semiconductor region; wherein, in an on-state operation, a channel of carriers of the second conductivity type is formed within the fourth semiconductor region along each of the at least two active trench regions; and wherein the second semiconductor region is configured to be conductivity modulated by second conductivity carriers injected from the third semiconductor region and first conductivity carriers injected from the first semiconductor region.
  2. 2 The bipolar semiconductor transistor according to claim 1, further comprising a fifth semiconductor layer formed between the first and second semiconductor layers, wherein the fifth semiconductor layer is of the second conductivity type and a doping concentration of the fifth semiconductor layer is greater than the doping concentration of the second semiconductor region.
  3. 3. The bipolar semiconductor transistor according to any preceding claim, wherein the at least one mesa trench comprises at least two mesa trenches separated in the second dimension.
  4. 4. The bipolar semiconductor transistor according to claim 3, wherein the at least two mesa trenches are configured to increase the doping concentration of the third semiconductor region.
  5. The bipolar semiconductor transistor according to any preceding claim, wherein the conductive layer of the at least one mesa trench is operatively connected to the second terminal.
  6. 6 The bipolar semiconductor transistor according to any one of claims 1 to 4, wherein the conductive layer of the at least one mesa trench is operatively connected to the control terminal.
  7. 7 The bipolar semiconductor transistor according to any one of claims 1 to 4, wherein the conductive layer of the at least one mesa trench is not operatively connected to any of the first, second and control terminals.
  8. 8. The bipolar semiconductor transistor according to any preceding claim, wherein a size of the separation between the at least one mesa trench and the at least two active trenches is smaller than about 2 micrometers in the second dimension and the doping concentration of the third semiconductor region is in excess of about 1 1016cm-3.
  9. 9 The bipolar semiconductor transistor according to claim 3, wherein a size of the separation between the at least two mesa trenches is smaller than about 2 micrometers in the second dimension and the doping concentration of the third semiconductor region is in excess of about 1 1016cm-3.
  10. 10. The bipolar semiconductor transistor according to any preceding claim, wherein the plurality of contact regions are operatively connected to the second terminal only in a region between the plurality of mesa trench regions.
  11. 11. The bipolar semiconductor transistor according to any preceding claim, wherein at least one dummy trench is placed adjacent to the at least two active trench regions in the second dimension, wherein the at least one dummy trench comprises a conductive layer operatively connected to the second terminal.
  12. 12. The bipolar semiconductor transistor according to any one of claims 1 to 10, wherein at least one dummy trench is formed adjacent to the at least two active trench regions in the second dimension, wherein the at least one dummy trench comprises a conductive layer operatively connected to the control terminal.
  13. 13. The bipolar semiconductor transistor according to any one of claims 1 to 10, wherein at least one dummy trench is formed adjacent to the at least two active trench regions in the second dimension, wherein the at least one dummy trench comprises a conductive layer that is not operatively connected to any of the first, second and control terminals.
  14. 14. The bipolar semiconductor transistor according to any preceding claim, wherein the bipolar semiconductor transistor is an Insulated Gate Bipolar Transistor (IGBT).
  15. 15. The bipolar semiconductor transistor according to claim 14 wherein the first semiconductor region comprises at least one region of the second conductivity type operatively connected to the high voltage terminal, and wherein the bipolar semiconductor transistor is a Reverse Conducting IGBT.
  16. 16. A method of manufacturing a bipolar semiconductor transistor, the method comprising: forming a first semiconductor region operatively connected to a first terminal, wherein the first semiconductor region is of a first conductivity type; forming a second semiconductor region over the first semiconductor region, wherein the second semiconductor region is of a second conductivity type; forming a third semiconductor region over the second semiconductor region, wherein the third semiconductor region is of the second conductivity type, and wherein a doping concentration of the third semiconductor region is greater than a doping concentration of the second semiconductor region; forming a fourth semiconductor region over the third semiconductor region, the fourth semiconductor region of the first conductivity type; forming at least two active trench regions which are extending from the fourth semiconductor region to the second semiconductor region in a first dimension, wherein the at least two active trench regions comprise an insulated layer and a conductive layer, and wherein the conductive layer is operatively connected to a control terminal; forming at least one mesa trench which are separated from the at least two active trench regions in a second dimension and which are extending from the fourth semiconductor region to the second semiconductor region in the first dimension, wherein the at least one mesa trench comprises a plurality of discrete mesa trench regions separated in a third dimension, and wherein the at least one mesa trench comprises an insulated layer and a conductive layer, the conductive layer operatively connected to the control terminal; forming a plurality of contact regions formed over the fourth semiconductor region which are operatively connected to the second terminal, wherein the plurality of contact regions comprises: at least one contact region of the first conductivity type formed between the plurality of discrete mesa trench regions in the third dimension; and at least one contact region of the second conductivity type formed between the at least one mesa trench and the at least two active gate regions; wherein a doping concentration of each of the plurality of contact regions is greater than a doping concentration of the fourth semiconductor region; wherein, in an on-state operation, a channel of carriers of the second conductivity type is formed within the fourth semiconductor region along each of the at least two active trench regions; and wherein the second semiconductor region comprises conductivity modulation by second conductivity carriers injected from the third semiconductor region and first conductivity carriers injected from the first semiconductor region.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165928A (en) * 2010-02-10 2011-08-25 Toyota Central R&D Labs Inc Insulated gate bipolar transistor
US20150206960A1 (en) * 2014-01-20 2015-07-23 Toyota Jidosha Kabushiki Kaisha Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165928A (en) * 2010-02-10 2011-08-25 Toyota Central R&D Labs Inc Insulated gate bipolar transistor
US20150206960A1 (en) * 2014-01-20 2015-07-23 Toyota Jidosha Kabushiki Kaisha Semiconductor device

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