GB2588750A

GB2588750A - Wafer

Info

Publication number: GB2588750A
Application number: GB1914988.9A
Authority: GB
Inventors: Ghadyani Zahra; Gibson Ursula; Balci Mustafa
Original assignee: Norfib As
Current assignee: Norfib As
Priority date: 2019-10-16
Filing date: 2019-10-16
Publication date: 2021-05-12
Also published as: GB201914988D0; WO2021074350A1

Abstract

A flat flexible semiconductor wafer for solar cell fabrication has an upper and lower surface, comprising: a plurality of coplanar and parallel semiconductor threads extending longitudinally through an inorganic insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein at least a portion of the threads are positioned sufficiently close to at least one of said upper or lower surface so that doping metal ions can diffuse into said threads when introduced to said upper or lower surface. The wafer is manufactured by arranging silicon fibres in parallel on a frame, applying a paste comprising dispersion of alumina, glass or quartz particles in a solvent and sintering.

Description

Field of the Invention

This invention concerns semiconductor wafers for use in photovoltaic applications, methods of making semiconductor wafers, and devices with semiconductor wafers.

Background

Conventional semiconductor wafers require energy intensive processes of refining semiconductor material to a solar grade ingot, which is then sawn to thin wafers. Such a process wastes large amounts of material and there is consequently a large loss in terms of energy, cost and materials.

Various attempts have been made to design 2D semiconductor materials which do not require such energy intensive processes. In particular, the use of semiconductor wires and other particles has been previously postulated.

US 2010/0159242 describes a plurality of photovoltaic 'canes' on a substrate. The canes comprise an electrode core, surrounded by an n-type core, then a p-type core, then cladding. The core is therefore not a semiconductor core since there is an electrode at the core. Such a construction is problematic, because it is difficult to achieve such delicate constructions for thin wires (e.g. <200 pm in diameter) on a commercially-viable scale. Any substantially 2D materials which feature these canes' are therefore bulky as a result. The materials are also not flat because of the round cross-section of the canes positioned on top of the substrate. Moreover, the entire document is speculative as it does not describe any working embodiments. US2010/0154877 is similar in its disclosure.

US2002/0109957 discloses a composition which features silicon balls in an adhesive layer. Compared to balls, drawing silicon core fibres is very well developed and can be easily scaled up. Annealing of the silicon core to single crystal is also easier for fibres, and therefore threads are more commercially viable. -2 -

US4913744 discloses certain wire like solar cells with electrodes at the core of the wire. These can be embedded in a semiconducting i-layer.

US2005/0218461 discloses integrated devices with wires having an electrode at the core.

FR2417188 discloses a plurality of semiconductor bars incorporated in a methacrylate transparent matrix doped with a fluorescent product. The bars have electrodes on them, also embedded within the matrix.

JPH07-335925 describes solar cell devices with silicon structures on a metal or metal oxide substrate. The semiconductor structures are all electrically joined together via metallic wiring situated between the semiconductor structures.

KR20130128832 discloses linear solar cells with conductive cores surrounded by semiconductor outer layers. These can be deposited, or wrapped, on/in a transparent insulating film.

Semiconductor wires can be made by melt-drawing the semiconductor, often in such a way that the core is glass-coated.

US2005/0000599 discloses a method for making glass-coated metallic alloy cores which involves forming a melt of the alloy in a hollow glass preform, drawing the glass preform to entrain and rapidly solidify molten alloy while simultaneously providing a glass coating, and compressing it during the drawing step. This enables the formation of coated articles with rectangular cross-sections which are more easily wound.

U2011/0103756 discloses a method of forming an optical fiber involving providing a preform having a core material and a glass cladding material surrounding the core material; drawing the preform at a temperature that is greater than the melting temperature of the core material to form a drawn fiber; and cooling the drawn fiber to form the optical fiber having a crystalline fiber core and a cladding that surrounds the crystalline fiber core and extends axially along a length of the crystalline fiber core. This document does not teach wafers, as it is merely concerned with fibres -3 -with a cladding extending along the length of the fibre. Furthermore, this document concerns fibre optic applications and does not focus on solar cell applications. It is thus in a different field.

US2011/0036123 discloses a method for glass coating wires.

JPS60-067908 discloses a method of drawing optical fibres with a conductor or semiconductor and a coating.

The methods of making the wires generally involve melt-drawing the wires individually.

The present inventors have surprisingly found that thin and flexible semiconductor wafers suitable for photovoltaic applications can be obtained by incorporating semiconductor threads within an insulator matrix. The wafers are also beneficial because at least a portion of the threads are positioned sufficiently close to at least one of the wafer surfaces so that doping metal ions can diffuse into said threads when introduced to said upper or lower surface, which enables solar processing after constructions of the semiconductor wafer. The doping of the threads can be carried out at the upper and/or lower surfaces of the wafer, and subsequent attachment of electrodes to the surfaces of the wafers enables the construction of solar cells, for example.

Such wafers are clearly advantageous over conventional semiconductor wafers which require sawing of an ingot to thin wafers, since the energy used is far less, as is the amount of waste semiconductor, which is expensive. The whole raw material is used efficiently in the present invention. In addition, much thinner wafers can be obtained compared to conventional semiconductor wafers so that flexible semiconductor wafers become feasible. A further advantage is an optimized efficiency over a wider range of incidence angle due to the cylindrical shape of the semiconductor threads.

Moreover, very thin threads can be used in the present invention, and therefore the corresponding wafer can be made thin and flexible, whilst still being robust and chemically resistant. Moreover, because the threads can be thin and the matrix can -4 -be transparent, semiconducting wafers which are translucent, transparent or partially transparent can be obtained. Furthermore, the positioning of the threads within the wafer enables top and bottom doping of the semiconductor thread for easy solar cell processing.

The invention also concerns methods to make thin wafers having semiconductor threads extending longitudinally through an insulating matrix. The methods surprisingly enable facile preparation of such wafers.

Summary of the invention

Thus, viewed from one aspect the invention provides a flat semiconductor wafer having an upper and lower surface, comprising: a plurality of semiconductor threads extending longitudinally through an insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein at least a portion of the threads are positioned sufficiently close to at least one of said upper or lower surface so that doping metal ions can diffuse into said threads when introduced to said upper or lower surface.

Viewed from another aspect, the invention provides a flat semiconductor wafer having an upper and lower surface, comprising: a plurality of semiconductor threads extending longitudinally through an insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein at least a portion of the threads are positioned within 500 nm of at least one of said upper or lower surfaces.

Viewed from another aspect, the invention provides a method of preparing a flat semiconductor wafer having an upper and lower surface, said wafer comprising: a plurality of semiconductor threads extending longitudinally through an insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein the method comprises the steps of: -5 -a) arranging a plurality of threads having a semiconductor core within an insulating matrix precursor, b) solidifying the product obtained in step a), preferably by sintering, to obtain the wafer.

Viewed from another aspect, the invention provides a photoelectronic device comprising a wafer as defined herein, preferably wherein said device is a photovoltaic device.

The features of the aspects and/or embodiments indicated herein are usable individually and in combination in all aspects and embodiments of the invention where technically viable, unless otherwise indicated.

Definitions The terms 'thread', 'wire' and 'fibre' can be used interchangeably herein. Such terms refer to a substantially elongate structure of substantially uniform diameter.

The term 'core' of the thread refers to the innermost portion of the thread. Thus, a thread having a semiconductor 'core' is one where the innermost portion of the thread is a semiconductor.

A 'flat' wafer refers to a wafer having upper and lower surfaces which are substantially planar. Such a surface may have grooves or other voids therein, but the overall geometry must be flat. 'Flat' excludes structures which have wires positioned on top of a flat surface, since the curvature of the cables would mean that the surface is not planar.

Where it is written that the threads 'extend longitudinally' through the insulation matrix, it means that the threads are embedded in the insulation matrix, and extend through it.

Where it is written that at least a portion of the threads are positioned sufficiently close to at least one of said upper or lower surface so that doping metal ions can diffuse into said threads when introduced to said upper or lower surface, it means -6 -that at least some of the threads have a region positioned close enough to an upper or lower surface to enable doping metal ions to be introduced into the threads under conventional doping conditions (e.g. diffusion furnaces).

Where it is written that a portion of a semiconductor thread is 'exposed' on the surface of a wafer, it means that the thread is not completely embedded within the insulation matrix, i.e. the portion of the thread is not completely covered by the insulation matrix.

By a group III-V (or type III-V) compound semiconductor is meant one comprising at least one element from group III and at least one element from group V. There may be more than one element present from each group, e.g. InGaAs, AlGaN (i.e. a ternary compound), AlInGaN (i.e. a quaternary compound) and so on. The same considerations apply to group II-VI semiconductors and group IV semiconductors.

Insulator matrix' and 'insulation matrix' are herein used interchangeably.

The upper and lower parts of the semiconductor threads are the portions of the semiconductor threads which are closest to the upper and lower surfaces of the wafer respectively.

Detailed description of the invention

The present invention concerns semiconductor wafers for use in photovoltaic applications Semiconductor threads The invention relies on the use of semiconductor threads which extend longitudinally through an insulation matrix.

Typically, the semiconductor core is selected from a type IV, type III-V, or type II-VI semiconductor material. Preferably the semiconductor core is selected from Si, GaAs, Ge, or alloys thereof, more preferably the semiconductor core is Si.

In a particular embodiment, the semiconductor is a solar grade semiconductor, -7 -preferably solar grade silicon. It will be appreciated that any semiconductor need not be completely stoichiometric as the possibility of doping exists, as discussed below. In some instances it is beneficial to intentionally introduce impurities to tune the properties of the semiconductor. In a further embodiment, therefore, the semiconductor comprises one or more additives, such as boron, aluminum, gallium, indium, phosphorous, arsenic, antimony, bismuth, lithium, germanium, tellurium, sulphur, tin, silicon, beryllium, zinc, chromium, selenium, magnesium, carbon, chlorine, sodium, iodine, fluorine, or hydrogen (e.g. hydrogen complexes passivating of Mg acceptors and by Mg self-compensation at higher concentrations), or any combinations thereof Such additives are typically present in amount of less than 10 wt% of the thread, preferably less than 5wtcYo of the thread, preferably less than 1 wt% of the thread, more preferably less than 0.1 wt% of the thread.

In a further embodiment, the semiconductor, which is typically silicon, is a solar grade semiconductor. In a particular embodiment, the semiconductor has a purity of at least 99.99% (4N), 99.999% (5N), 99.9999% (6N), preferably at least 99.99999% (7N), more preferably at least 99.999999% (8N), more preferably at least 99.9999999% (9N).

In a particular embodiment, the semiconductor has a bulk minority carrier diffusion length of at least 20 pm, preferably at least 30 pm, more preferably at least 35 pm, such as in the range of 20-80 pm, 30-60 pm, or 35-50 pm. Typically, the threads have a bulk minority carrier diffusion length of around 40 pm. Such bulk minority carrier diffusion lengths and mobilities are comparable to those of single-crystal silicon. Minority carrier lifetime can often be a more accurate parameter for indicating the solar grade [Martinsen, Bulk fabrication and properties of solar grade silicon microwires, APL Materials 2, 116108 (2014)]. Longer diffusion lengths generally result in better solar cell performance. Due to the small size of silicon threads, common minority carrier lifetime and diffusion length measurement methods result in small signals. In this case sensitive measurement techniques like Electron Beam Induced Current (EBIC) is used to measure minority carrier lifetime and diffusion length of silicon threads. -8 -

Typically the semiconductor is crystalline. By crystalline is meant micro-or nano-crystalline, polycrystalline, or a substantially single-crystal semiconductor material. The term "substantially" is used in describing the semiconductor core to take account of the fact that semiconductor materials normally contain at least some internal or surface defects either inherently or purposely added, such as lattice defects or a few grain boundaries. The term substantially also reflects the fact that certain dopants may distort or otherwise affect the crystal structure of the semiconductor material.

Typically, the threads of the invention have a semiconductor core thickness in the range 2-300 pm, preferably 5-200 pm, more preferably 10-150 pm. Such thicknesses enable the formation of thin structures which are flexible, light and which utilise small amounts of raw material. By thickness is meant the longest cross-sectional dimension, or, for threads with circular cross-sections, the diameter.

There is no particular limit on the length of the semiconductor threads: these can be at least 1 mm, at least 1 cm, or at least 10 cm in length, for example.

In a particular embodiment, the threads of the invention have a substantially circular cross section. By 'substantially' it is meant that there is a variance of less than 30%, preferably less than 20%, 10%, or 5 °/o in the diameter. Such a cross section results in an optimized efficiency over a wider range of incidence angle. A circular cross-section still covers the case where a small amount of the semiconductor has been removed at the upper and/or lower surface of the wafer by chemical/physical processes.

In a particular embodiment, the wafer has at least one intermediate cladding layer surrounding the thread core and extending axially along a length of the semiconductor core. Typically, said cladding is glass. Such a cladding can be present on commercially obtained semiconductor wires. Such an intermediate cladding can be removed or thinned by laser ablation. For the method involving a) arranging a plurality of threads having a semiconductor core within an insulating matrix precursor, and b) solidifying the product obtained in step a), preferably by sintering, to obtain the wafer; the insulating cladding may be removed or thinned by laser ablation prior to step a). -9 -

Insulation matrix Typically, the insulation matrix is an inorganic insulation matrix. Inorganic matrices are preferred since these are more robust for the outdoor conditions faced by solar cells, and are better able to withstand the harsh processing methods for the preparation of the wafers and for the doping (e.g. using diffusion surfaces) of the semiconductor threads. The wafers are advantageous over wafers/films which have organic insulating matrices, since organic materials tend to exhibit faster degradation when used in solar cells, and are less likely to be able to withstand the harsh processing conditions associated with, for example, doping.

In a preferred embodiment, the insulating matrix is a quartz matrix, an alumina matrix, or a glass matrix, or mixtures thereof, preferably a quartz or alumina matrix, most preferably quartz. The insulating material should be carefully selected so that it can withstand the thermal and mechanical shocks during the processes of the invention and does not contaminate the semiconductor threads. Furthermore, the insulating matrix should preferably be chosen such that it is able to withstand the outdoor climate conditions which are faced by photovoltaic cells.

It is clear that when glass-coated threads are used in the preparation of the solar cell, there will be some glass present in the insulator matrix. Thus combinations of quartz, alumina and glass can be used in the insulator matrix.

Typically, the insulator matrix is transparent.

Wafers A key advantage of the wafers of the present invention is that at least a portion of the semiconductor threads (typically the thread semiconductor cores) are positioned sufficiently close to at least one, preferably both, of the upper and/or lower surface so that doping metal ions can diffuse into said threads when introduced to said upper or lower surface. The skilled worker is able to appreciate at what distance this occurs; the required distance between the wafer and the surface will depend on the nature of the semiconductor, the nature of the dopant, the nature -10 -of the insulation matrix, and the conditions used to dope. The doping of semiconductors is well known in the art.

In a particular embodiment, at least a portion of the threads are positioned sufficiently close to both of said upper and lower surface so that doping metal ions can diffuse into said threads when introduced to said upper and lower surface.

Having the threads sufficiently close enables doping of the wafers to be carried out after embedding of the threads within the wafer. Selective top and bottom doping of the thread can thus be performed, and solar preparation can be done once the semiconductor threads are embedded in the matrix.

In a particular embodiment, at least a portion of the threads (typically the semiconductor cores of the threads) are positioned within 500 nm (e.g. at a distance of 0-500 nm) of at least one, preferably both, of said upper or/and lower surfaces. In a further embodiment, at least a portion of the threads are positioned within 500 nm of at least one, preferably both, of said upper or/and lower surfaces so that doping metal ions can diffuse into said threads when introduced to said upper or/and lower surface. In a particular embodiment, at least a portion of the threads are positioned within 500 nm of both of said upper and lower surfaces, typically so that doping metal ions can diffuse into said threads when introduced to said upper and lower surfaces. In further embodiments, the threads are positioned within 200 nm, within 100 nm, within 50 nm, within 25 nm or within 10 nm of the upper and/or lower surfaces. These distances (within 500nm, within 200 nm etc.) typically refer to the shortest distance between the surface of the wafer and the outer surface of the thread semiconductor core. In essence, therefore, the distances described above refer to the distance between the semiconductor core and the surface.

In a particular embodiment, the entirety of the semiconductor threads are positioned sufficiently close to at least one, preferably both, of the upper or lower surface so that doping metal ions can diffuse into said threads when introduced to said upper or/and lower surface. Similarly, the entirety of the semiconductor threads can be positioned within 500 nm of at least one, preferably both, of said upper or/and lower surfaces, typically so that doping metal ions can diffuse into said threads when introduced to said upper or/and lower surface.

Typically, the wafers of the invention have a thickness in the range 1-500 pm, preferably 2-300 pm, preferably 5-200 pm, more preferably 10-150 pm. Such structures are flexible, light and utilise only small amounts of raw material.

In a further embodiment, the wafers can be much thicker, e.g. with a thickness in the range 150-1000 pm, e.g. 150-800 pm. Further suitable thicknesses therefore include 1-1000 pm, 2-800 pm or 5-500 pm.

The exposure of the semiconductor threads can be done by patterning, as is shown in Figure 4, i.e. without the need to completely remove the entire surface of the wafer.

In a further embodiment, the overall area occupied by the semiconductor cores of the threads amounts to less than 50% of the total area of the wafer; such as less than 40%, less than 30%, less than 20%, or less than 10% of the total surface area of the wafer. [NB: the area occupied by a core is calculated as thickness (e.g. longest cross-sectional dimension) x length; if the core has a circular cross section, the area is calculated as diameter x length]. This ensures good transparency of the film.

In a further particular embodiment, the threads (typically the semiconductor cores of the threads) are separated from one another by a distance at least equal to the longest cross-sectional dimension of the threads (e.g. diameter if the threads are circular). In a further particular embodiment, the semiconductor threads are not electrically connected to one another via a conducting element embedded in the insulation matrix. In a further particular embodiment, the threads are separated from one another in the insulation matrix by the insulation matrix material only. In a further particular embodiment, the semiconductor cores are separated from each other only by insulating matrix and, if present, insulating cladding.

Because the semiconductor threads are typically thin, the wafers of the invention are typically transparent to the naked eye. In a particular embodiment, therefore, -12 -the wafer is transparent or semi-transparent. In a further embodiment, the wafer is translucent or transparent. By transparent is meant herein that at least 50% of light traverses through the wafer, e.g. at least 90%, at least 95% or at least 99%, without scattering. By semi-transparent is meant herein that 10-50% of light traverses through the wafer.

Typically, the threads in the wafer are coplanar, and are preferably substantially parallel. In a particular embodiment, at least 20% of the threads are substantially parallel with each other.

Preferably, the wafer of the invention is flexible, i.e. mechanically deformable. This is beneficial since it enables the preparation of flexible photovoltaic devices.

In a particular embodiment, the semiconductor threads and the insulation matrix make up at least 90 wt% of the wafer, preferably at least 95 wt% of the wafer, more preferably at least 99 wt% of the wafer. In a further embodiment, the wafers of the invention consist of the semiconductor threads and the insulation matrix. In a further embodiment, the wafer does not include any conductive or metallic materials, such as metallic wiring, in the insulation matrix. If there is intermediate cladding around the semiconductor core, e.g. a glass cladding, this is considered to be part of the semiconductor thread for the purposes of the percentages described in this paragraph.

In a further embodiment, the semiconductor threads make up at least 90 wt%, preferably at least 95 wt%, more preferably at least 99 wt%, more preferably at least 99.9 wt% of the semiconducting and conducting components in the wafer. In a further embodiment, the semiconductor threads make up at least 90 °/0, preferably at least 95 %, more preferably at least 99 %, more preferably at least 99.9 % of the semiconducting and conducting components in the wafer, wherein the percentages refer to percentages of the number of semiconducting and conducting components in the wafer.

Preferably, the wafers are free of any electrodes embedded within the insulator matrix. This does not exclude any electrodes attached to the top and/or bottom of the wafers to generate photovoltaic devices using the wafers.

-13 -In a particular embodiment, at least a portion of the threads are exposed on the upper and for lower surface of the wafer.

Doping It is within the scope of the invention for the threads to be doped. Doping typically involves the introduction of impurity ions into the threads. These can be introduced at a level of up to 1021/cm3, such as up to 1020/cm3, up to 1013/cm3, or up to 1018/cm3. Usually 1019/cm3 is sufficient for solar application, however for ohmic contacts a thin layer of p+ or n+ can be used that has doping ions in an amount of around 1021/cm3. The threads can be p-doped or n-doped as desired although as noted below it is possible for an undoped region to be present. Doped semiconductors are extrinsic conductors whereas undoped ones are intrinsic.

Extrinsic semiconductors with a larger electron concentration than hole concentration are known as n-type semiconductors. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. N-type semiconductors are created by doping an intrinsic semiconductor with donor impurities. Suitable dopants to form n-type semiconductors include phosphorous, arsenic, antimony, bismuth, lithium, tellurium, sulphur, tin, silicon, germanium, selenium, carbon, indium, aluminium, chlorine, gallium, iodine, fluorine, or any combinations thereof.

More specifically, suitable dopants to form n-type semiconductors may include: phosphorous, arsenic, antimony, bismuth, lithium for n-type silicon; tellurium, sulphur (substituting As), tin, silicon, germanium (substituting Ga) for n-type gallium arsenide; tellurium, selenium, sulphur (substituting phosphorus) for n-type gallium phosphide; silicon (substituting Ga), germanium (substituting Ga), carbon (substituting Ga, e.g. naturally embedded into MOVPE-grown layers in low concentration) in n-type gallium nitride, Indium gallium nitride, and Aluminium gallium nitride; indium, aluminium (substituting Cd), chlorine (substituting Te) in n-type cadmium telluride.

-14 -gallium (substituting Cd), iodine, fluorine (substituting S) in n-type cadmium sulfide.

The p-type semiconductors have a larger hole concentration than electron concentration. The phrase 'p-type' refers to the positive charge of the hole.

In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. P-type semiconductors are created by doping an intrinsic semiconductor with acceptor impurities. Suitable dopants to form P-type semiconductors include boron, aluminum, gallium, indium, beryllium, zinc, chromium, silicon, germanium, zinc, magnesium, fin, beryllium, zinc, chromium, hydrogen (e.g. hydrogen complexes passivating of Mg acceptors and by Mg self-compensation at higher concentrations), phosphorus, lithium, sodium, or any combinations thereof.

More specifically, suitable dopants to form p-type semiconductors may include boron, aluminum, gallium, indium for p-type silicon; beryllium, zinc, chromium (substituting Ga), silicon, germanium (substituting As) for p-type gallium arsenide; zinc, magnesium (substituting Ga), tin (substituting P) for p-type gallium phosphide; beryllium, zinc, chromium (substituting Ga), silicon, germanium (substituting As) for p-type gallium arsenide; zinc, magnesium (substituting Ga), fin (substituting P) for p-type Gallium phosphide; magnesium (substituting Ga), hydrogen (e.g. hydrogen complexes passivating of Mg acceptors and by Mg self-compensation at higher concentrations) for p-type gallium nitride, indium gallium nitride, and aluminium gallium nitride phosphorus (substituting Te), lithium, sodium (substituting Cd) for p-type cadmium telluride; lithium, sodium for p-type cadmium sulfide.

In a typical embodiment, at least a portion (i.e. at least some) of the threads have a p-n or p-i-n junction. Furthermore, the wafers of the present invention allow for doping to be carried out at the upper and lower surfaces. Typically, the p-type region of the semiconductor is on (or near) one surface of the wafer and the n-type -15 -region is on (or near) the other surface of the wafer. This means that electrodes can be attached to the wafer surfaces to either the p-or the n-regions of the semiconductor threads. Compared to strands which are axially doped (e.g. having an N-type core and outer P-type shell), the doping can be carried out in one step for all of the threads together, e.g. by using a diffusion furnace and a suitable doping precursor. The processing of the wafer to a solar cell can thus be carried out in minimal steps. Furthermore, since an electrical connection can be made to the surface of the wafer and does not have to be made to individual threads, relatively large electrodes can be used and the manipulation of the device is facilitated.

In a further embodiment, however, the invention covers axially-doped threads, i.e. having an axial p-n or p-i-n junction, e.g. threads with a p-type core and an n-type shell.

Devices In a further embodiment, the invention provides a device comprising the wafer of the present invention. Such a device is preferably an electronic device, more preferably a photoelectronic device, most preferably a solar cell. Such devices have the potential to be efficient, cheap and flexible at the same time Typically, in the device of the present invention, the wafer further comprises an electrode on at least one surface of the wafer in electrical contact with at least a portion of the semiconductor threads.

The device of the present invention preferably comprises the wafer as herein described and at least one electrode on at least one surface of the wafer in electrical contact with p-type or n-type regions of the semiconductor threads. Typically, the device will have two electrodes, preferably one on either side of the wafer. Most typically, since the p-type region of the semiconductor is typically on one surface of the wafer and the n-type region is on the other surface of the wafer, one electrode will be in electrical contact with the p-type region of the semiconductor threads on one surface of the wafer, and the other electrode will be in electrical contact with the n-type region of the threads on the other surface of the wafer.

-16 -Clearly, once an electrode is added to the exposed surface of the semiconductor thread, the surface might no longer be 'exposed' to the outside environment, but it will be nonetheless still be exposed in the sense that it is not covered by the insulation matrix.

In contrast to traditional solid solar grade semiconductor ingots, even less raw material is used by incorporating semiconductor threads through just a portion of the wafer. Light trapping techniques can be utilized to keep the same efficiency.

Manufacturing methods In a further aspect, the invention also provides a method of preparing a flat semiconductor wafer having an upper and lower surface, said wafer comprising: a plurality of semiconductor threads extending longitudinally through an insulating matrix, preferably an inorganic insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein the method comprises the steps of: a) arranging a plurality of threads having a semiconductor core within an insulating matrix precursor, b) solidifying the product obtained in step a), preferably by sintering, to obtain the wafer.

The semiconductor core is typically crystalline.

Step b) is preferably a step of sintering the product obtained in step a) to obtain the wafer. The insulator matrix precursor in such an embodiment is typically a plurality of particles of the insulator matrix material.

Sintering is well-known in the art and is a process of compacting and forming a solid mass of material by heat or pressure. In such an embodiment, the insulator matrix precursor in step a) is preferably selected from quartz particles or alumina particles. Such particles can be provided as a dispersion. Heat and/or pressure is applied in step b) to obtain the wafer by sintering. Typically, sintering occurs at a temperature of 500-1400 °C, preferably 700-1100°C. If the particles are provided in -17 -a dispersion, an initial drying step at 150-200°C can be used prior to the sintering at higher temperatures.

In case of assembling and binding semiconductor core threads in the method described above, any intermediate cladding can be removed or thinned by laser ablation before assembling and binding the threads.

In all method aspects of the invention, the methods can further comprise a step of: c) removing parts of the upper and/or lower surfaces of the wafer using -a chemical process such as etching, -a physical process such as abrasive polishing, laser ablation, or reactive ion etching, or -a combination of a chemical and physical process such as CAIBE etching; preferably such that wafers as described herein and in the claims are obtained. In a particular embodiment, removing parts of the upper and/or lower surfaces of the wafer is done such that at least a portion of the threads are positioned sufficiently close to at least one of said upper or lower surface so that doping metal ions can diffuse into said threads when introduced to said upper or lower surface. In a further particular embodiment, removing parts of the upper and/or lower surfaces of the wafer is done such that at least a portion of the threads are positioned within 500 nm of at least one of said upper or lower surfaces, such as within 200 nm, within 100 nm, within 50 nm, within 25 nm, or within 10 nm of at least one of said upper or lower surfaces.

In a particular embodiment, removing parts of the upper and/or lower surfaces of the wafer is done to expose at least a portion of the threads at the upper and/or lower surface of the wafer. Preferably, removing parts of the upper and/or lower surfaces of the wafer is done to expose a portion of the threads at both the upper and lower surface of the wafer.

In all method aspects of the invention, the methods can further comprise a step of: d) doping the upper and lower parts of the threads to form a p-n or p-i-n junction. Such doping is typically performed in a diffusion furnace, which typically requires temperatures of 700 °C or more, such as 800 °C or more or 900 °C or more, e.g. temperatures of 700-1500°C, 800-1400°C or 900-1300°C. The doping involves bringing the exposed semiconductor surface in contact with a dopant precursor, -18 -and then using the diffusion furnace to introduce the dopant into the semiconductor. Typical materials used for both N-type and P-type doping are described above.

Steps a)-d) described above are typically carried out in order.

In a further embodiment, any intermediate cladding layer, if present, is removed by chemical etching, e.g. using HF. Such a removal can be performed between stages a) and b) for the first method, or before stage a) for the second method.

In a particular embodiment, the methods of the present invention are for preparing any flat semiconductor wafer as defined herein, or in the claims, where technically viable.

Description of the Figures

Figure 1 shows a schematic representation of a wafer with a semiconductor thread extending through an insulation matrix.

Figure 2 shows a schematic representation of a wafer with a semiconductor thread extending through an insulation matrix, wherein the surfaces of the semiconductor threads have been exposed at the upper and lower surfaces of the wafer.

Figure 3 shows a schematic representation of a device with the wafer of the invention, the wafer having been p-and n-doped at the upper and lower surfaces of the wafer, and electrodes in contact with the upper and lower surfaces of the wafer.

Figure 4 shows a schematic representation of a wafer according to the present invention where the inner semiconductor threads have been exposed by patterning.

Figures 5a and 5b show the arrangement of Si threads in a Teflon assembly apparatus.

Figure 6 shows the application of an alumina dispersion onto the Si threads -19 -Figure 7a/7b show wafers obtained after heat treatment at 900 °C and polishing.

Figure 8a/8b show wafers obtained using glass as the insulator matrix.

Examples

A method for making a semiconductor wafer from silicon core threads Glass-cladded silicon core fibres were arranged in a Teflon-coated frame as in Figures 5a/5b. A paste with Alumina particles dispersed in a solvent is applied on top of the silicon fibres as shown in Figure 6 (Resbond 989FS, from Cotronic, a high purity alumina ceramic precursor, was used as the paste). After drying at room temperature and a thermal step below 200 °C (usually 150-200 °C), the wafers were robust enough to be taken out of the frame. Additional heat treatment at 900 °C ensured a more robust wafer for polishing from both sides (as shown in Figure 7).

A similar method can be used to assemble fibres in a glass or quartz dispersing material (as shown in Figure 8).

Claims

-20 -Claims 1. A flat semiconductor wafer having an upper and lower surface, comprising: a plurality of semiconductor threads extending longitudinally through an insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein at least a portion of the threads are positioned sufficiently close to at least one of said upper or lower surface so that doping metal ions can diffuse into said threads when introduced to said upper or lower surface.
2. A flat semiconductor wafer having an upper and lower surface, comprising: a plurality of semiconductor threads extending longitudinally through an insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein at least a portion of the threads are positioned within 500 nm of at least one of said upper or lower surfaces.
3. A flat semiconductor wafer as claimed in claim 1 or 2, wherein the insulating matrix is inorganic.
4. A flat semiconductor wafer as claimed in any preceding claim, wherein at least a portion of the threads are exposed on the upper and/or lower surface of the wafer.
5. A flat semiconductor wafer as claimed in any preceding claim, wherein the overall area occupied by the semiconductor cores of the threads amounts to less than 50% of the total area of the wafer.
6. A flat semiconductor wafer as claimed in any preceding claim, wherein the wafer is transparent.
7. A flat semiconductor wafer as claimed in any preceding claim, wherein at least a portion of the threads have a p-n or p-i-n junction. -21 -
8. A flat semiconductor wafer as claimed in claim 7, wherein the p-type region of the semiconductor threads is on one surface of the wafer and the n-type region is on the other surface of the wafer.
9. A flat semiconductor wafer as claimed in any preceding claim, wherein the semiconductor core is crystalline.
10. A flat semiconductor wafer as claimed in any preceding claim, wherein said wafer is flexible, i.e. mechanically deformable.
11. A flat semiconductor wafer as claimed in any preceding claim, wherein the semiconductor threads have a bulk minority carrier diffusion length of at least 20 pm, preferably at least 30 pm, more preferably at least 35 pm, such as in the range of 20-80 pm, 30-60 pm, or 35-50 pm.
12. A flat semiconductor wafer as claimed in any preceding claim, wherein the semiconductor core is selected from a type IV, type III-V, or type II-VI semiconductor material, preferably the semiconductor core is selected from Si, GaAs, Ge, or alloys thereof, more preferably the semiconductor is Si
13. A flat semiconductor wafer as claimed in any preceding claim, wherein the thickness of the wafer is in the range 2-300 pm, preferably 5-200 pm, more preferably 10-150 pm.
14. A flat semiconductor wafer as claimed in any preceding claim, wherein the inorganic insulating matrix is a quartz matrix or an alumina matrix.
15. A flat semiconductor wafer as claimed in any preceding claim, wherein the wafer has at least one intermediate cladding layer surrounding the thread core and extending axially along a length of the semiconductor core, preferably wherein said cladding is glass.
16. A flat semiconductor wafer as claimed in any preceding claim, wherein the semiconductor cores are separated from each other only by insulating matrix, and, if present, intermediate cladding.-22 -
17. A flat semiconductor wafer as claimed in any preceding claim, wherein the threads have a substantially circular cross section.
18. A flat semiconductor wafer as claimed in any preceding claim, wherein the insulator matrix is transparent.
19. A flat semiconductor wafer as claimed in any preceding claim, wherein the threads are coplanar, and are preferably essentially parallel
20. A method of preparing a flat semiconductor wafer having an upper and lower surface, said wafer comprising: a plurality of semiconductor threads extending longitudinally through an insulating matrix; wherein the semiconductor threads have a semiconductor core; wherein the method comprises the steps of: a) arranging a plurality of threads having a semiconductor core within an insulating matrix precursor, b) solidifying the product obtained in step a), preferably by sintering, to obtain the wafer.
21. A method as claimed in claims 20, further comprising a step of: c) removing parts of the upper and/or lower surfaces of the wafer using -a chemical process such as etching, -a physical process such as abrasive polishing, laser ablation, or reactive ion etching, or -a combination of a chemical and physical process such as CAI BE etching; such that wafers according to any of claims 1-19 are obtained.
22. A method as claimed in any of claims 20-21, further comprising a step of: d) doping the upper and/or lower parts of the threads to form a p-n or p-i-n junction.
23. A method as claimed in any of claims 20-22, wherein any intermediate cladding layer, if present, is removed by chemical etching, e.g. using HF.-23 -
24. A method as claimed in any of claims 20-23, wherein the flat semiconductor wafer is as claimed in claims 1-19.
25. A method as claimed in any of claims 20-24, wherein the semiconductor core is crystalline
26. A photoelectronic device comprising a wafer as claimed in claims 1-19, preferably wherein said device is a photovoltaic device.
27. A device as claimed in claim 26, wherein the wafer further comprises an electrode on at least one surface of the wafer in electrical contact with at least a portion of the semiconductor threads.