GB2586632A - Method of submodule switching control in modular multilevel converters - Google Patents

Abstract

A bidirectional modular multilevel converter (MMC) comprises a plurality of submodules 107-112, each configured to switch between at least two switching positions, and at least one energy storage element. A predetermined voltage is output by determining changes to the switching position of each submodule. The determination is based on at least one of: a switching history of each submodule or group of neighbouring submodules, the location of each individual submodule from a reference point, the temperature of each submodule or group of neighbouring submodules, the voltage or energy output of each individual energy storage element, the health condition of each submodule, and the functionality of each submodule. The energy storage element of each submodule may be a capacitor or a battery. The MMC may comprise at least one phase unit, each having at least two phase arms, each comprising two or more submodules connected in series. The MMC may monitor the output energy of each phase arm, calculate a balancing circulating current using a minimisation function, apply this to at least one phase arm to balance the energy output so that the switching frequency of submodules across each phase arm is equalised, and the number of changes to the switching position of submodules is minimised.

Description

Method of Submodule Switching Control in Modular Multilevel Converters

Field of Invention

The present disclosure is in the field of modular multilevel converters, and in particular how to increase the efficiency of such converters and reduce the size and cost of such converters.

Background

The most important requirement of MMC modulation is to guarantee stability of modulation that compromises balancing the converter energy due to the submodules capacitor voltages in MMC arms at any condition, including normal and abnormal operations. In High Voltage High Current (HVDC) applications, the number of MMC submodule capacitors can exceed 200+ submodules per converter arm. Hence, it is vital to have a robust mechanism for switching submodules together with voltage balancing methods that can provide satisfactory performance at both normal and abnormal operational conditions of the MMC.

In addition to balancing MMC submodule capacitors voltages, it is very important financially to reduce MMC switching frequency across all its submodules -this has significant impact on converter footprint and environmental impact, losses and the life-time of MMC hardware including switches, submodule capacitor, and protection circuit, to name a few. It is thus important to reconsider combined problems of MMC submodule switching frequency control and submodules capacitor voltage balancing to manage and control costly interactions.

Existing methods are focused on "average switching frequency" across the arm submodules, and do not handle control of individual submodules switching control. The latter compromise is a part of this disclosure. This disclosure teaches a method that uses the history of the switching commands and prediction of submodules capacitor voltages leading towards reduced switching frequency across the arm submodules as well as generating circulating currents to balance submodules capacitor voltages of the converter arm. As results of this disclosure, high-performance converter modulation as well as reduction at the size and cost of the converter will be two major advantages of this disclosure.

This disclosure also discloses second Quadratic Optimization (QP) method for submodules capacitor voltage balancing using optimized circulating currents. This disclosure is related in fact to decoupling submodules switching frequency and submodules balancing optimization using two quadratic optimization methods -combining both optimization could result in very complex and highly nonlinear optimization. However, with the methods disclosed in the patent, the two optimization are separated with a specific format of QPs for both submodule and circulating current for balancing submodules voltages.

Summary of this disclosure are as follows:

* Submodules switching logic is selected based on dynamical operation of the converter (and not just the submodule capacitor voltages). It includes all submodules capacitor voltages, arm voltages, arm current and minimizing power losses and switching frequency.

* The results of this proposal will lead towards increased efficiency/performance and/or reduction at the size of submodules capacitors (and their protection/... circuits).

* Different submodules can be penalized at different switching rates -e.g. switching at higher-level stacks can be higher than those of lower-height submodules, or old submodules (are near to the end of their life expectancy) can be chosen to be switched less frequently than newer submodules; this will be a great achievement for maintenance (e.g. to replace failed parts of submodules or complete submodule, fibre connections, etc), operation time, and most importantly the safety measures due to risks for working at height. Having considered reachability of submodules, while the average of all submodules switching frequencies are the same, submodule switching at higher-stacks are higher than those of lower level. So, lifespan of higher stacks will be increased.

Art Background

There are prior arts on MMC switching and circulating current control for PWM based modulations. MMC with PWM modulation are suitable for low voltage and limited medium voltage application and is not suitable for HVDC systems. Due to many submodules in the converter arms for HV applications (e.g. HVDC), PWM modulations are not admitted and rather staircase modulations are to be applied at such MMC HVDC applications due to two main reasons: * Reduction of switching in staircase modulation is more challenging due to managing switching large number of submodules that is one problem addressed in this disclosure.

* PWM switching is much expensive than staircase modulation for HV and most MV applications due to power losses and footprints.

Prior arts with regards to PWM based modulation, are based on selective harmonic elimination, use of a range of pulse width modulation (PWM) and Space-Vector PWM (SVPWM) strategies, use of different sorting methods, use of range of different MMC topologies e.g. cascaded H-Bridge multilevel active rectifier, and use of the voltage balancing/drift mechanism to name a few. However, these are effective for MMC with PWM based switching with fewer number of submodules. Having said this, MMC for medium voltage (MV) applications use PWM based modulations, C. D. Townsend, et al, "Optimization of Switching Losses and Capacitor Voltage Ripple Using Model Predictive Control of a Cascaded H-Bridge Multilevel StatCom", in IEEE Trans. On Power Electronics, Vol. 28, No. 7, pp. 3077-3087, July 2013. Such medium-power MV MMC applications include only limited number of submodules and hence reducing converter arms switching frequency and hence converter footprints is not a major issue at MV MMC systems. Other PWM based methods have been used on MV applications, J. Janning, J.-C. Mercier, "Medium voltage three-level inverter for high speed applications," in Proc. 12th European Power Electronics and Applications Conf. (EPE 2007), Aalborg, 2007, pp. 1-10. As said, selective harmonic elimination PWM has been applied to the MMC, lowering the switching frequency requirements for given harmonic performance, G. S. Konstantinou, M. Ciobotaru, V. G. Agelidis, "Operation of a Modular Multilevel Converter with selective harmonic elimination PWM," in Proc. 8th IEEE Int. Power Electronics Conf. & ECCE Asia, 2011, pp. 999-1004. Optimized Pattern Pulse (OPP) methodology is also a strategy to choose a switching pattern that is used to minimize MMC harmonic contents with PWM techniques, J. E. Huber and A. J. Korn, "Optimized Pulse Pattern modulation for Modular Multilevel Converter high-speed drive," 15th International Power Electronics and Motion Control Conference (EPE/PEMC), Novi Sad, 2012, pp. LS1a-1.4-1-LS1a-1.4-7.

This disclosure teaches a method for HVDC MMC with staircase modulation that covers both HVDC and MVDC applications with any level of voltage or power.

The switching frequency control has never been applied to the MMC staircase-modulation including HVDC VSC applications. There have been some works by prior arts to reduce "average switching frequency", but not in the course of control of individual submodules switching frequency. Besides, they have had many limitations and drawbacks, including Tolerance Band Modulation, A. Hassanpoor, "A multilevel converter with cells being selected based on phase arm current," PCT/EP2012/073699. This disclosure does not suffer from the same limitations as the above work by A. Hassanpoor and other prior art in the field of the future of MMC switching. The main limitations of the published tolerance band method are as follows: * Tolerance band method is only concerning within converter arm, using converter arm current. It does not handle two or more arms, hence Tolerance band method is missing an inter converter arm balancing.

* Tolerance band method is not using history of submodules switching commands, nor the modulation switching time window, which is the one feature discussed in the

present disclosure. * * * *

Tolerance band method is not addressing some of the same problems, namely the optimization of MMC AC grid and DC grid quantities, for example minimizing the MMC arm reference voltage tracking error along with other features of the present disclosure.

Tolerance band method operates based on the current zero crossing assumption. This may be severely violated at the faults due to current large dc components and/or zero-sequence portion of fault currents. That is, Tolerance band method is unable to control MMC modulation or submodules switching under faulty operations.

Tolerance band method uses parameter called tolerance band but no mathematical relationship is built that is valid on the effect of the tolerance band on switching frequency.

Tolerance band method is not addressing discriminated submodule frequency control. Thus, it cannot control the switching frequency of each submodule individually; even reducing the arm average switching frequency is questionable as it is dependent variable of the capacitor voltage balancing.

Summary of the Invention

Aspects of the present invention are set out in the independent claims. Optional features are set out in the dependent claims. The present description of the Figures is intended to teach the person skilled in the art one or more ways of implementing the invention. For the avoidance of doubt the description below is not intended to be limiting in any way, and any features that are taught in any way to be essential, either explicitly or implicitly, that are not contained within the features of the independent claims, are not considered essential.

One embodiment may comprise a method for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, using a modular multilevel converter comprising a plurality of submodules, each submodule configured to switch between at least two switching positions, and each submodule comprising at least one energy storage element, the method comprising: determining one or more changes to the switching position of each submodule to output the predetermined voltage, wherein said determination is based on a switching history of each submodule or collective group of neighbouring submodules. This may have the effect of reducing the switching frequency for each submodule, and therefore reducing the amount of maintenance of the MMC required, and increasing the lifetime of the submodules.

A further embodiment may comprise a method for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, using a modular multilevel converter comprising a plurality of submodules, each submodule configured to switch between at least two switching positions, and each submodule comprising at least one energy storage element, the method comprising determining one or more changes to the switching position of each submodule to output the predetermined voltage, wherein said determination is based on the location of each individual submodule from a reference point. This may have the effect of increasing the lifetime of more difficult to reach submodules to save on time required to perform maintenance.

A further embodiment may comprise a method for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, using a modular multilevel converter comprising a plurality of submodules, each submodule configured to switch between at least two switching positions, and each submodule comprising at least one energy storage element, the method comprising determining one or more changes to the switching position of each submodule to output the predetermined voltage, wherein said determination is based on the temperature of each submodule or the temperature of a collective group of neighbouring submodules. This may have the effect of keeping all of the submodules within an efficient working temperature range to avoid damage.

A further embodiment may comprise a method for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, using a modular multilevel converter comprising a plurality of submodules, each submodule configured to switch between at least two switching positions, and each submodule comprising at least one energy storage element, the method comprising determining one or more changes to the switching position of each submodule to output the predetermined voltage, wherein said determination is based on the voltage or energy output of each individual energy storage element. This may have the effect of not overloading the capacitor which in turn may increase the lifetime of the submodule.

A further embodiment may comprise a method for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, using a modular multilevel converter comprising a plurality of submodules, each submodule configured to switch between at least two switching positions, and each submodule comprising at least one energy storage element, the method comprising determining one or more changes to the switching position of each submodule to output the predetermined voltage, wherein said determination is based on the health condition of each submodule, and the functionality of each submodule. This may have the effect that submodules in better health condition perform more switching to reduce the maintenance required.

A further embodiment may comprise a modular multilevel converter for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, the modular multilevel converter comprising a plurality of submodules, each submodule configured to have at least two switching positions, and each submodule comprising at least one energy storage element, and a controller, wherein the controller element is configured to perform the method of any of the above embodiments.

A further embodiment may comprise a method of calculating optimum circulating currents for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage for a phase arm, using a modular multilevel converter comprising one or more phase units connected between a first terminal and a second terminal, wherein the phase units each comprise two phase arms separated by a third terminal; wherein each of the arms comprises two or more of the submodules connected in series, each submodule configured to have at least two switching positions, and each submodule comprising at least one energy storage element, wherein the method comprises the steps of: monitoring the output energy of each phase arm; calculating a balancing circulating current using a minimisation function; applying the balancing circulating current to at least one phase arm to balance the energy output of each phase arm, so that the switching frequency of submodules across each phase arm is equalised, and the number of changes to the switching position of submodules is minimised. A further embodiment may comprise a modular multilevel converter to implement this method.

A further embodiment may include a system incorporating a modular multilevel converter, wherein portions of the converter are held from a ceiling area of a structure such that they do not contact the ground; wherein converter is split into levels, each containing one or more of the submodules, and wherein a first level of submodules is closer to the ground than a second level of submodules, wherein the height of each submodule is used to determine the submodules to be switched to output the predetermined voltage.

A further embodiment may incorporate a computer program product, or a tangible, non-transitory computer readable medium to implement any of the above methods.

To attempt offering a compact solution that will also overcome the shortcomings and limitations of the prior art, the present disclosure may enable the minimization of switching frequency, minimization of the converter arm reference voltage tracking error, and reduction of the submodules capacitor voltages ripples based on: 1) One or more steps of switching history 2) Present arm current and submodules capacitor voltages, and 3) One or more steps ahead of predicted submodules capacitor voltage, that leads to a compact format of a Quadratic programming portfolio.

This presented disclosure can apply to a wide range of MMC VSC applications including HV, MV and LV levels with any number of submodules per converter arm. In HVDC MMC applications, however, the benefits of reducing footprints and converter power losses are more dominant, which will make this disclosure more applicable to HVDC MMC design solutions.

One aim of the present disclosure is to find a switching sequence for the MMC that should compromise between arm submodules capacitor voltage variation (around submodule capacitor nominal voltage), arm reference voltage tracking error, and minimizing (average) switching frequency of the stacks. This will turn out that energy of MMC arms are balanced in an optimal fashion.

Some of the contributions of this disclosure are as follows: 1-Submodules switching logic is selected based on dynamical operation of the MMC (and not just the submodule capacitor voltages as per conventional switching methods). It includes all submodule capacitors voltages, converter arm voltages, arm current and minimizing switching frequency and power losses, to name a few.

2-The results of this disclosure will lead towards increased efficiency/performance and even reduction in the size of MMC including submodule capacitors and their protection circuits.

3-This disclosure lets individual submodules or different submodule stacks be switched at different frequency rates by selecting different penalizing QP design parameters-e.g. switching at higher-level stacks (or those submodules that are near to the end of their life expectancy) can be penalized more than those of lower-height stacks; this will be a great achievement for maintenance (changing failed submodules, broken or failed fibre connections, etc), operation time, and most importantly the safety measures due to risks for working at height. (While the average switching frequency of all submodules can be similar, submodule switching at higher-stacks are to be lesser than those at lower-level stacks. This leads to increased reliability of converter operation due to switching submodules or stacks that are located at height.

Statement of the Problem

This disclosure provides optimized MMC modulation that controls submodules switching frequency, satisfactorily track the arms voltage references, and control the submodules capacitor voltage ripples, at both normal and faulty conditions. One concept taught in this disclosure is simply to formularize the problem of MMC modulation to make the converter balanced in an optimal fashion. This disclosure proposes methods to find a switching sequence of the MMC stacks submodules by converting the submodules switching into a cheap optimization format, that can be applied to both half-and full-bridge HVDC MMC VSCs. One compact mathematical optimization solution proposed within this disclosure may tackle three main performance indexes of the MMC regarding the arms submodules switching: 1) Minimize submodules capacitor voltage ripples s (variances, deviations, or offsets), i.e. to retain submodules capacitor voltages around their nominal voltages with a designated variation penalized by parameter q within the optimization cost function; 2) Minimize arm reference voltage tracking error (i.e. to better track the arm reference voltage that is provided by high-level controller, to deliver appropriate active and reactive power profiles); and 3) Minimize submodules average or distinguished switching frequency.

The latter minimization is very important at high-power high-voltage applications, including HVDC MMCs. The teachings of the present disclosure may allow one to specify design optimization parameters to impose different average frequencies at different submodules. For instance, if the temperature of a submodule pack is increased for any reason (due to e.g. post-fault failure or end of life concerns), the proposed method could reduce the frequency of that defective submodule(s). This results in the fact that some critical submodules will switch at lower frequencies compared to other healthy units. This is not possible with any of existing MMC balancing and switching approaches as explained in more detail below.

Some of the differences of the present disclosure as compared to existing MMC modulation methods are as follows: 1-Use switching history as a time-window, which will result in minimized submodule switching frequency. Existing approaches do not address this functionality.

2-This disclosure applies to balancing of one, two (vertical), three (horizontal) or all six arms of MMC. Existing approaches only apply to one single converter arm.

3-This disclosure applies to both normal and abnormal operations. Existing methods can handle only normal condition.

4-This disclosure handles individual submodule switching frequency tuning, so the switching frequency is independently controllable. Existing methods do not handle independent submodule frequency control.

5-This disclosure covers submodule capacitor voltage variation as a direct byproduct of the mathematical optimization that are solutions to a Quadratic Programming problem. Existing methods are not capable of this feature.

Brief Description of the Drawings

FIG 1(a) shows a submodule structure within the half-bridge modular multilevel converter (MMC) arm.

FIG 1(b) shows a submodule structure within the full-bridge modular multilevel converter (MMC) arm.

FIG 2(a) shows the schematic of a submodule structure within either the half-or full-bridge 15 MMC.

FIG 2(b) shows the schematic of a submodule energy element (or capacitor) as a dc voltage source, within either the half-or full-bridge modular multilevel converter (MMC) arm.

FIG 3 shows the schematic of an arm structure with group of submodules within either the half-or full-bridge MMC.

FIG 4 shows the general schematic of a converter arm acting as a dc voltage source, compromising n submodules (cells) either the half-or full-bridge submodules.

FIG 5 shows horizon of switching position for a half bridge submodule (left), and the affected horizon of the submodule capacitor voltage FIG 6 shows the MMC submodules switching state flow including the past, present and future switching positions, U. and submodules capacitor voltages, V. FIG 7 shows the structure of MMC with six that may use at least one of the disclosed methods for control of the switching of an individual submodule or group of submodules in MMC three phases using staircase modulation FIG 8 shows the block diagram illustrating the control of switching of an individual 30 submodule or group of submodules in an arm of MMC MVDC with staircase modulation.

FIG 9 shows the block diagram illustrating the control of switching of an individual submodule or group of submodules in an arm of MMC HVDC with stair case modulation.

FIG 10 shows the structure of MMC with circulating current optimization block.

FIG 11 shows the simulation results of arm A+ submodules instantaneous capacitor voltages together with average of them at normal operation.

FIG 12 shows the simulation results of the given arm reference voltage (Vref) and the actual converter arm voltage for arm A+, at normal operation.

FIG 13 shows the simulation results of arm current and balancing current for arm A+, at normal operation.

FIG 14 shows the simulation results of submodules frequency of arm A+ together with the average arm switching frequency, at normal operation.

FIG 15 shows the controlled switching position and measured capacitor voltage of an individual submodule within arm A+, at normal operation FIG 16 shows the simulation results of arm A+ submodules instantaneous capacitor voltages together with average of them at faulty operation, subjected to a fault at time t=0.5 secs.

FIG 17 shows the simulation results of the given arm reference voltage (Vref) and the actual converter arm voltage for arm A+, subjected to a fault at time t=0.5 secs.

FIG 18 shows the simulation results of dc current at de side, subjected to a fault at time t=0.5 secs.

FIG 19 shows the simulation results of submodules frequency of arm A+ together with the average arm switching frequency, subjected to a fault at time t=0.5 secs.

Detailed Description

With the structure of single submodule or group of submodules (e.g. an arm of converter) shown in Figs. 2-4. One concept of the present disclosure is for submodules switching using staircase MMC modulation is described in Fig. 5 for half-bridge applications. The same idea can be applied to full bridge MMC.

This disclosure can be applied to both half-bridge and full-bridge converters, at both normal and abnormal (faulty) operational conditions. It is noted that the terminology of "arm" may often be called "branch", "stack", or "limb portion".

One concept of this disclosure is to look at the time window of the MMC switching consequences that includes past and present switching commands. As shown in Fig. 5, based on the direction of the arm(s) current(s), if an individual submodule capacitor voltage is predicted to be remaining within its allowed boundaries, then the submodule switching status is not to be changed at the next sample time, i.e. if submodule capacitor is bypassed (u=0) at the current time instant (610), it will remain bypassed at the next sample (630, 650), and the same if it was switched in (620), it will be kept switched in (640, 660). This turns out that the submodules switching frequency is minimized in line with the MMC control specifications. It is worth mentioning that this is only one part of the mathematical optimization portfolio that is covered in this disclosure. There are two more factors i.e. minimizing submodules capacitor voltage ripples and minimizing converter arm reference voltage tracking errors that are also covered in the compact optimization format as disclosed in this disclosure.

This disclosure on submodules switching control has many advantages, e.g. it can reduce maintenance time at MMC HVDC higher stacks. Lower level submodules have higher average switching frequency, while higher levels will have lower average frequency. This results in the fact that risk of failure at top submodules are considerably minimized. In MMC HVDC converters (real-life systems), massive number of submodules are piled (stacked) at top of each other, which usually reach the building ceiling at very high. While lower submodules (from height point of view) can be easily accessed (to be tested or replaced due to e.g. fibre optic link failure) if needed, higher levels submodules are very difficult to be accessed from the ground level. At occasions that technicians need to access top submodules, they must use ladders to access them at height. This turns out that often takes much longer times to carry out those tests/maintenance/... at height. This has several disadvantages, such as prolonged maintenance -while the converter must be tripped (retained out-of-service), and yet there are severe safety concerns to be considered.

Use of Switching History Let consider the switching state flow of an MMC in Fig. 6, which includes arm submodules capacitor voltages (vi) and submodule switching commands (u). Note that 'n' can be the number of submodules either as a group or all within one converter arm, or submodules within any combination of two or more arms of the MMC.

Note that this disclosure may be applied to the submodules switching within an individual converter arm (branch), or two or more arms (A+, A-, B+, B-, C+, C-) at the same time. With the arm reference voltages and arm currents measurements at time k, the switching sequence U(1) are derived; each element is integer, i.e. {0,1} for half-bridge and {-1,0,1} for full-bridge MMC. Vectors and matrixes are shown in bold in this disclosure.

The aim is to find the nominated submodules' optimum switching sequence at the next step k+1 as the best available switching signals, via minimizing a mathematical cost function.

This disclosure finds the "best" switching signals to be applied to the converter arm submodules, in half-bridge or full-bridge fashion, so that the designated cost function is minimized.

Concept of Optimizing MMC Submodules Switching As illustrated in Fig. 6, it only considers states transition from time k to time k+2. This disclosure may be applied to minimize the L2-norm of the following errors: * U(k+1)-U(k) This is the error between the converter arm switching sequence at current time k and next step time k+1. By this, we minimise the changes at switching positions of each n submodules (vector of n-by-1) to be done by the L2-norm, so the switching frequency is minimised. For n submodules of one arm or more arms, the weighted sum of the squared of this error will be =r @it L" I = rIIU(k + 1) -U(k)1122 where U(k)=[11,(k) 1112(k) I ** * I t (k)I is the submodules switching commands at time k.

* Vref(k+1) -Ur(k+1)V(k+1) This is the error (scalar) between the arm reference voltage and that of sum of all contributing submodules capacitor voltages. By doing this, we also include minimization of the tracking error of the converter arm(s) reference voltage given the converter arms reference voltages. For n submodules of one arm or more arms, the weighted sum of the squared of this error will be Ire°Y V ref 11! L+, lk, = y(V ref (k +1)-U (k +1)T V (k +1))2 k+1 1=1 where it can be considered as instantaneous, average or RMS over the control time period, Tc.

* V(k+2) - 1 is an n-by-1 vector of ones, given the nominal voltage of the submodule capacitor, , the submodules measured capacitor voltages and the arm current at time k, this term is the error between predicted submodule capacitor voltage at time step k+2 and the submodule capacitor nominal voltage. By minimising this term, the goal is to optimise submodules switching in a way that the active submodules capacitor voltages will be kept near their nominal voltages, 7, hence reducing submodule capacitor voltage ripples. It results in an n-by-I column vector error and our aim is to minimize the L2-norm or the error sum of squares (SSE). For n active submodules at one arm (or more arms), the sum of the squared of this error will be kit = ql1V(k + So, the proposed optimization disclosure considered a compromise for improving MMC performance with regards to all three qualities as mentioned above, which are minimizing arms submodule capacitors voltage ripples, minimize switching frequency, and minimize the converter arm(s) reference voltage tracking error.

In Fig. 6, the time index is shown as II? and converter submodule variables are as follows: - V(k) are the converter arm submodules capacitor voltage vector at discrete time t = k, and - U(k) are the converter arm submodules switching commands, where U(k) need to be a binary or integer vector such as II e { 0, l}" for Half-Bridge MMC or U e {-I, 0, i}" for Full-Bridge MMC At time k, the submodule capacitor voltages, V(k), are known as per converter pre-charged MMC pre-charging procedure. The first switching vector at time k, U(k), can be arbitrarily selected by converter controller. By measuring the converter arm current, and having the converter arm switching vector, it is possible to predict the submodule capacitor voltages at the next steps using e.g. the first-order Euler approximation: V(k +1).-V(k)+ -' i(k)U(k) (' rz- (1) V(k +2) V(k +1)+-51(k)U(k +1) ,V(k)+ a;,U(k)+ U(k +1) Ana% n To be detemmxi where Ts is the sampling time, C is submodule capacitor value, i(k) is the converter arm current at time k, V(k) is the measured voltages of all submodules at time k, and V(k-Fl) is the predicted voltage of the submodules at time k+1.

Note that we have used approximation of 1(k)=1(k+1). This is a valid approximation because due to the phase reactors, as they do not let arm currents pose abrupt changes. This approximation can be further improved or predicted as well based on the rate and existing value of current, using e.g. the first order Euler method.

As Eq. (1) shows the predicted voltages of submodules at time k+2 are function of history of submodules switching that are at time k and k+1. This means, an U(k+1) will change the submodules capacitors voltages and we are looking at those switching patterns that will minimize the capacitors voltages ripples or deviations from nominal voltages, i.e. keep them around their nominal.

Also, note that in Eq. (1), C is assumed here to be constant for all submodules energy element capacitors -it can be different for different submodules without any problem, which means that the disclosure is capable to distinguish between different capacitors, e.g. old capacitors vs new ones, etc. Thus, health condition discrimination is a one concept of the present disclosure.

For smaller sampling times, Eq. (1) is enough for submodule capacitor voltage predictions.

However, other numerical methods, like bilinear transform (or Tustin's method), can also be employed at this end. If capacitor sizes are different, then C will be formulated accordingly, but often this is ignored. Also, switching sampling time at the MMC low-level power electronics control are around a few psecs for which Euler first-order approximation will provide sufficiently accurate prediction for submodule capacitor voltages. However, without loss of generality, the same concept can be applied for the cases that sampling time is larger and need other accurate numerical approximations, such as bilinear (Tustin) methods, etc. We assume there is only one converter arm. This can be extended to two, or more arms without loss of generality.

The one-step ahead can be extended to a larger prediction time window as shown below for which a similar optimization can be derived: V (k +1) = V (k)+ a(k)U(k) k =1, 2, (2) with a(k)==i(k)and i(k) is the arm current at time k, Ts is the switching sampling time and C is the submodule capacitor value.

One aim of the present disclosure is to optimize MMC's three key factors: G1-Minimize the arm average switching frequency given as 01 Ipresent -11 I past. )2 that is i=1 the sum of the squared of differences between the switching positions of two subsequent time steps. Here we show only for one-step ahead for simplicity, i.e. from k to k+1; similarly, this may be extended to the wider time windows, with more prediction steps.

This has never been used at the MMC switching frequency control applications with staircase-modulation applications.

G2-Minimize the converter arm reference voltage tracking, i.e. minimize the sum of the V2 Vreflwhere present present Ipresent i=1 Vref is the present converter arm reference voltage; G3-Minimize the total submodules capacitor voltage ripples i.e. Lute 17)2 (v that is the sum of the squared of the submodules capacitor voltage ripples, i.e. variations of submodules capacitor voltages from their nominal voltages; 'n' is the number of nominated submodules in a group or at least one converter arm. These nominated submodules are referred to as "To Be Determined" (TBD) in this disclosure, as the status is unknown and must be provided by optimization as disclosed in this disclosure.

where V is the submodule capacitor nominal voltage.

With the above three minimization objective cost elements, with weighting optimization parameters for individual submodule or group of submodules in arm, the optimal MMC switching problem is converted to the following cost function criterion: squared errors (differences) of given by J, = rt(41 'presentpast -11) Tc SMs switching changes _ E*v.

sent 147 'present 'present i-1 Arm reference voltage tracking error -Eq1(17, Lim -2 SMs capacitor voltage tipples Vref * P (3) where optimization (penalties) design parameters are some positive numbers as follows: - r for minimizing the submodules average switching frequency; -y: for minimizing arms reference voltage tracking error; - q: for minimizing submodules capacitor voltage ripples; and - T0: Optimization sample period.

For simplicity, throughout the remaining of this document, we will use the format of Eq. (3) where the optimization parameters will be shown as scalars for an arm. However, equation (3) can also use varying weights for individual submodule or group of submodules, as shown below in Eq. (4): tz nt p sent)2 + ( qi future -7)2 = ri (z111 I)2 ± y(Vrefl 1 1=1.

present past present pr 1=1 P,=1 (4) It is also noted that one (out of three weighting parameters, i.e. r, y, and q) is a free optimization parameter. This means that we could use only two parameters as optimization weighting parameters and let the third parameter be unity. The results of optimization solutions i.e. next submodule(s) switching commands, will be identical.

Eq. (3) shows the average of the cost function over Tc period. Tc can compromise different time periods including instantaneous sampling, i.e. Tc=Ts (switching sample time), or cover averaging over the AC grid period (Tc=1/f), to name a few. J, can also be considered at sample-based cost function, i.e without integration or averaging.

The optimisation parameters i.e. r, y and q, are positive real number or tuned based on the operation of MMC.. They can also be manually controlled (like a nob) by an operator if needed, e.g. at MMC commissioning tests.

As said, the above optimization design parameters (r, y and q) can be constant or may be adaptive in real-time for reducing overall cost function, leading towards reduced submodules switching frequency and enhanced MMC operation. For instance, for submodules average switching frequency control (or individual submodules frequency), r must be tuned. In case the above penalizing gains are to be adaptive, i.e. tuned in real-time, relevant measurements and tuning procedures will be used. For instance, if the arms average switching frequency is to be retained between Vino, fmad then will be adapted accordingly in order to control the switching frequency of all or particular submodules. For instance, if the temperature of a candidate submodule is higher than expected for any reason, the associated submodule switching penalty is increased that will reduce its average switching frequency.

Initial parameters for r, y, q can be chosen arbitrary and automatically tuned with start of converter modulation. These parameters are adaptable/tunable automatically, e.g. use of their droops, at both normal and abnormal converter operational conditions, based on the voltage, voltage rate, arm current, and/or arm current rate.

Note that the MMC modulation optimization parameters in Eq. (7) can be constant or adaptive (controlled). For controlled modulation, if for instance we consider MMC dynamic transition only one step ahead, i.e. from time step k to k+1, for controlling switching frequency of all or specific submodules, the switching frequency optimization parameter 71 will be a vector whereas the relevant optimization term will be rr( -) k+1 j=1 This results in the following quadratic: [AU, [T R[A1.1]]=[U(k+1)-U(k)f R[U(k +1)-U(k)], where R=diag(r), j=1,...,n.

In a similar fashion and at MMC normal operating status, the given penalty gains can be set higher for submodules that are located at different height levels for reducing maintenance times at higher stacks. For example, if average frequency of the MMC is to be, say, 60Hz, one can specify lower submodules to have 80Hz and higher levels to have 40Hz switching frequencies. The outcome of the average MMC switching frequency will be kept at the designated 60Hz. This is an example for an indicative idea. However, one goal of this disclosure is that these are possible with this disclosure and has not been considered by any other existing MMC switching approaches.

The above optimization design parameters can be associated with individual submodules. In this case, r, y and q will be changed to matrix parameters e.g. in matrix diagonal format of diag{qi,q2,...,q,} where submodule capacitor voltage ripples are optimized individually or for a group of submodules. Similarly, this can be done for r and y can be considered; the same procedure of this disclosure could be applied without loss of generality.

In addition to these performance limits, the main objective of any optimization within this disclosure (including the one disclosed presently) is to guarantee that all submodule capacitor voltages will be kept within the allowable min-max voltage levels, that is: k =1, 2,...

Using Eq. (2) at time k=0, the voltage limits at time k=2 will be: 1/"." < V(2) = V(0) +6); U(0) +o U(1) ( V", -V(0)-q,U(0)) < 17(1)-(V",,," -V(0)-o;U(0)) for cl#0 If al=0, that means 1=0, i.e. the associated submodule is switched out or bypassed and its capacitor should remain at the same voltage level (i.e. not charging nor discharging), hence easily controller will pose th=0.

The above will result in a compact constrained format of LB (1(1) tiB (5) This means that the constraints with regards to submodules voltages charging/discharging is converted to constraining switching commands to Eq. (5) that will be used in this method. Thus, switching optimization for MMC modulation should guarantee that this inequality will be satisfied at every sample time.

From Eq. (2) and inequalities of Eq. (5), the present optimization can be subjected to Au h, where the real-valued inequality constraints matrix boundaries of A and b are functions of submodule capacitor voltages limits, i.e. V,-,,;" and V,"," as given above.

The optimization problem in Eq. (4) can be expressed as the following cost criterion: A(k)= r1111(k)-U(k -1)11; + 7( Vref(k)-U(k)1 V (k))1 + '1111 (k + (6) with k = 1, 2, ... , and Ilxll, is the L2-norm (or the Euclidean norm) of vector x.

One of the design parameters (q, r and y) in Eq. (6) can be removed without affecting on the results of optimization. In this case, the scaling gains of must be cost function will be normalized but the results of the minimization will be the same at both cases.

Eq. (6) is solved at each time step k' that will result in the optimal switching sequence, U(k), leading towards minimization of the cost function of Eq. (6). In fact, by providing optimal switching U(k), there will be MMC performance compromises between the all three cost functions based on the given optimization design parameters as defined in G1, G2, and G3 above.

Using the governing dynamics of submodule capacitor in Eq. (2), the inequalities of Eq. (5) and the cost function of Eq. (6), the minimization problem leading towards optimal switching sequences, U, at the next time step k+1 will be converted into a compact format of the Integer Quadratic Programming (IQP) Optimization as follows: min =1 (1,1 II,U,+ .11 s I A,U, (7) U, E {0,1}" ORI-1,0,11" where H1 and f1 are functions of parameters of Eq. (3), arm currents, arm submodules capacitor voltages, and initial switching commands U0.

Eq. (7) for small number of submodules, can be solved readily to provide global optimisation of MMC modulation. Methods like Semidefinite Programming (SDP) relaxations, Approximation and integrality gap, Branch and bound for exact solutions, Cutting plane method and Randomized rounding are practically suitable for MMC MV applications with fewer number of submodules that can only be feasible solution to be applied only to small-size converters, like MVDC MMC with fewer number of submodules per arm.

For large numbers like MMC HVDC it is NP-hard and hence need a solution that are

disclosed later in this disclosure.

Fig. 7 illustrates the first embodiment of this disclosure with global optimisation based on Eq. (7) that includes a group of submodules that are connected in series in at least one arm (107,108,109,110,111,112). Two arms (one upper or positive, and one lower or negative arm) build a phase of MMC, that are connected between first and second DC terminals (VDC+, VDC.) that are separated by an AC terminal. Each positive (upper) converter arm of particular phase is connected to negative (lower) arm of the same phase via reactor L. The mathematical optimisation of Eq. (4) is embedded at (114), where the arms voltage references are provided by external control (113) and initial optimisation parameters r, y and q are provided by (115).

Fig. 8 illustrates the first embodiment of this disclosure with global optimisation based on Eq. (7) for one arm that includes a group of submodules that are connected in series in top (positive) arm of the phase A. which is connected to the first DC terminal. The mathematical optimisation of Eq. (7) is embedded at (114) for an arm only, where the A+ arm voltage references are provided by MMC higher level control or external control (113). (710) is the delay unit that holds the history of switching sequence LIA+.

U1 are the next switching submodules commands for MMC modulation as decision variables that are integer numbers (0,1) for half-bridge MMC and {-1,0,1} for full-bridge MMC.

An example with one step ahead results in the following values with given arm current and submodules capacitor voltages at time k: a = -C' urn, = present H, -(r + qa2)1, + yVp,""/Vp1,.",,", qa13 -YV ref present Vprecent -rU past where Vc, is the submodules capacitor voltages at present time (k), i is the measured present arm current, I is an n-by-1 column vector of ones, 1"is the n-by-n identity matrix where in' is the number of TBD submodules in the arm.

Note that H1 is symmetric positive semidefinite and easily invertible matrix, hence the optimization has always solution.

This compact quadratic optimization of Eq. (7) disclosed herein, is to provide compact formulate of Eq. (7) that will result in best possible MMC modulation for deriving desired arms submodules switching sequence following the desired performance criteria as per 20 MMC performance given in the aspects of G1, G2, and G3 above.

Any quadratic optimization method that could solve Eq. (7) will provide optimal submodules switching sequence e.g. at the next time step k+1 and, repeating similarly for the future time steps.

Any optimized MMC modulation derived from any mathematical method or numerical methods will be a solution to Eq. (7). In any case, it will be Integer Quadratic Programming Portfolio Optimization. For HB MMC, it can also be a Binary quadratic programming problem. - (8)

As an alternative solution, optimisation of Eq. (7) can be converted to standard form by eliminating inequalities by using e.g. Interior-Point method with barrier function by which inequalities are converted to logarithmic barrier term. However, these methods are suitable for MMC with very a few submodules. There are also other approaches such as evaluation strategy, cutting plane method, Heuristic, Branch-and-Bound and CPLEX methods. However, these are only suitable for small MMC VSCs.

Fast Switching Suboptimal Solution to the Quadratic Optimization in Eq. (7) This proposed mathematical optimization to the problem of MMC Modulation i.e. submodules switching as of Eqs. (7)-(8) is NP-hard for which sub-optimal solutions can be employed for practically cost-effective, fast and with less computational burdens. real-valued switching control actions, U(t), can also be employed as a replica of integer switching signals in an unconstrained QP manner. Our simulations have confirmed that such sub-optimal solutions are very promising for high power MMCs like HVDC applications. Simulation results have shown that the MMC performance can be significantly improved at different operating conditions, including normal operation and abnormal (under fault) conditions.

Having said this, the proposed mathematical optimization finds automatically the "best" i.e. optimum possible switching sequence at any converter operating conditions.

Via Eqs. (1-8), the proposed optimal MMC modulation leading towards best (dynamic) submodules switching is converted to a constrained QP problem that can be solved by numerous signal processing and data analysis methods. Methods may utilize floating-point data formats to accommodate large matrices inversion, which takes the source code in C programming software and generates highly efficient embedded codes.

The QP as of Eq. (7) is an integer constrained quadratic programming problem. Existing processing and computational may not be able to solve in real-time for global optimal switching commands U1. However, this disclosure offers a pragmatic solution that is feasible for practical MMC applications with optimization relaxation steps as follows: As original optimization problem of Eq. (7) may not be practically solved in appropriate computational frames in real time for MMC HVDC applications with larger the aim will be to provide a suboptimal solution to the Constrained Integer Programming as of Eq. (7). To this end, one element that may be used in a numerical solution will be matrix inversion of Hi.

The matrix Hi is "symmetric matrix" and also has a unique structure. So, this is important as it can help matrix inversion computationally feasible. Also, it is important to realize that it has always inversion. Therefore, it is guaranteed that matrix inversion will be an issue.

The method to address the problem MMC modulation as resulted in Eq. (7) are summarized next: One suboptimal solution to Eq. (7) is detailed in Method 1 that leads to the following Unconstrained Quadratic Optimisation for real-valued switching signals. As detailed in Method 1, the main goal of fast suboptimal optimization for MMC HVDC applications with larger number of submodules is to build and solve the simple unconstrained optimization problem in unconstrained real manner where the switching actions are obtained as real numbers from the following QP: 711 1 2 u J1 r bri T (9) s.t. U1 E R"red where H1 and f1 are given e.g. Eq. (8) for reduced number of submodules, nredn, as detailed in Method 1.

Either QP is to be solved at the original format of Eq. (7) for a global minima, or approximated for suboptimal switching commands U1 as of Eq. (9), inversion of matrix H1 will be inevitable. For MMC with fewer submodules, matrix inversion can be fast and pragmatic. For MMCs with large number of submodules, like MMC HVDC, it is important to calculate inverse of Hi promptly in real time.

Fig. 9 illustrates the first embodiment of this disclosure with fast suboptimal optimisation based on Eq. (9) and Method 1 for one arm that includes a group of submodules that are connected in series in top (positive) arm of the phase A, which is connected to the first DC terminal. The mathematical optimisation of Eq. (9) is embedded at (114) for an arm only, where the A+ arm voltage references are provided by MMC higher level control or external control (113). (710) is delay unit that holds the history of switching sequence 1144-, and (830) is the quantizing/tweaking block.

In case, the quadratic optimization was real and unconstrained, the solution of the unconstrained suboptimal optimization of Eq. (9) will be: U; (10) Since H1 is a real, symmetric and positive definite matrix, there are always solution to the matrix inversion. This means the method will provide solutions to submodules switching commands. The optimization will provide switching solutions (commands) to the problem of MMC staircase-modulation under any converter circumstance, including particularly startup, normal operation, faulty situations, and low voltage fault-ride-through (LVRT) scenarios to name a few.

While numerical solutions like the Cholesky decomposition could be used in calculation of Hi matrix inversion for the above suboptimal unconstrained QP, this method offers use of Woodbury Matrix Identity to solve Eq. (10) as a fast approach for real-time purposes: (A -FBCD) =24' -24-1B(C-1 D24-1 B)-' DA' (11) By applying Eq. (11) to Eqs. (8) and (10) for matrix inversion, we have: A = A, B =V C = AI, D =VI (12) FI'=(A+AVVT)1 = -mArl (Vr),41-1 A. 01 -1 +A(17,,' A_1 VD) The above will provide fast analytical solution to the Hi matrix inversion, hence practically the quadratic optimization is viable for MMC staircase modulations including HVDC systems.

In Eq. (12), please note that: 1-In is an identity matrix of size n-by-n, where n is the number of arm(s) submodules.

2-From Eq. (8), A-1 is simply calculated; Note that A is a diagonal matrix, A=diag{ai} (a1>0)4 Al = diag{1/4 3-The matrix inversion of Hi is converted to a simple algebraic Eq. of (10). This will let real-life HVDC MMC system (with large number of submodules), compromising one arm (or more arms simultaneously), be tackled by this method.

4-yr 0 (optimization scalar parameter), from Eq. (8): ADO; this means ve[A iv° >-0 and thus m r 0 (scalar). This means the inversion of matrix H1 always exists -this guarantees that the methods disclosed herein will provide stable HVDC MMC modulation at all time that is very vital for practical applications.

With the idea of using Woodbury Matrix Identity, one can solve the Quadratic Optimization as of Eq. (7), where the complex MMC switching is converted into simple algebra! Hence, there will be no need for complex costly computations.

The next step will be to convert the results of above real QP by quantization to discrete-time integer numbers, i.e. {0,1} in half-bridge and {-1,0,1} in full-bridge MMCs. This is done by considering a threshold as explained in Method 1. Tweaking process is to compensate for the loss of quantization error due to conversion from integer to real QP. The aim is providing fast solution to the problem of MMC modulation that reduces the diversity of switching patterns. If this solution is used, the optimal switching modulation results (U1) are quantized to the nearest integer values; i.e. will be rounded to {0,1} for the half-bridge MMC and for full-bridge they will be rounded to {-1,0,1}. By relaxation switching, it is possible to reduce the integer-to-real numeric conversion errors, hence helping to the fast suboptimal MMC modulation to get closer to the original optimal switching optimization as disclosed herein as per Eq. (7). Thus, relaxation of submodules switching commands are carried out to compensate for reducing quantization error due to conversion from integer to real QP that is needed for the purpose of providing fast solution to the original problem of NP-hard MMC modulation as of Eq. (7).

Method for MMC Switching Control with Staircase Modulation (First Embodiment) Method 1 illustrate the detailed flowchart of the proposed compact quadratic optimization (QP) with submodules switching control. This covers the disclosure on control and/or minimising converter submodules switching frequency, individually or in a group, using staircase MMC modulation.

Method I: Fast Suboptimal Switching Control of MMC HVDC Input: MMC modulation parameters (N, C, Ts, Tc, vmin, vmax, vnom, Imin, lmax, f, ...); Set initial weights of each QP parameter (r, y, q and p); Set time k=0; Input: Receive Vref (reference of arm voltage) at time k; Input: Obtain measurements of submodules capacitors voltages, arm current, and current switching positions; Build LB and UB for allowable min/max values of switching in real numbers (Eq. 5); In temporarily variables, from Eq. 2 calculate the predicted voltages of all submodules capacitors by considering each and every TBD submodule; Nominate those cells that, if are assumed to be switched in, their predicted voltages will exceed submodule capacitor voltage boundaries as calculated in Step (2); Detach submodules that must be (kept) switched out at time k+1. Disregard these submodules from the optimization; Detach submodules that must be switched in at time k+1; sum up their capacitor voltages to update the new Vref; Disregard these submodules from optimization; Determine the approx. number of submodules needed based on new Vref, as nred =(Vref_new/vnom) approximate number of TBD submodules; Build H1 and f1 (Eq. 7) for TBD submodules for calculation of their switching positions; Solve Unconstrained Quadratic Optimisation (Eq. 9) for reduced number of submodules, nredn, for real-valued U*(k+1); Sort the U*(k+1) and determine the threshold from Step (3); Complete integer quantization on U*(k+1) to U(k+1) for TBD switching positions.

Augment the TBD switching positions with detached switching positions and send all to controller to use for the next submodules switching at the next sample time; Tune OP weighting parameters, if needed; Time step k F k+1; Go to: Step 1; Optimum Circulating Current to Balance Converter Arms (Second Embodiment) After obtaining solution to the optimization problem of Eq. (7) as optimal switching for MMC modulation, the second embodiment of this disclosure is to calculate the circulating current that will help balance MMC arms i.e. to balance MMC submodules capacitor voltages or energies; this will result in smooth operation of MMC and will help further reduce switching frequency at next steps. To this end, assume that there are three independent balancing currents, Ix, ly, and lz and we wish to calculate three converter arm balancing currents as shown in Fig. 10.

As shown in Fig. 10, the idea is to find three circulating currents Ix, ly, and /z that will balance MMC arms by optimizing of synchronized minimization of submodules switching frequency, arms reference voltage tracking error and submodule capacitor voltage ripples.

To find the MMC optimal circulating currents, this discloses a new constrained quadratic optimization programming as given in Eq. (7): mini, T -2 - -s.t. 1-7n < /2 < /rx (13) 12min < 17' < 17 where H,, f, are calculated similarly from Eqs. (1)-(7) with one additional term for each converter arm that is new alpha: = I". +I, I a, -Eq. (13) can be converted to constrained quadratic optimization with only one constraint, by the use of e.g. Euler first order approximation: mini, 1 H,I,+ f,7 I, (14) s.t. max(i2nun, /2 mint/rx, Ian?, ± Ines) Eq. (14) can apply to single phase (with two positive and negative arms), or to three phases (6 arms) of MMC. In case of three phase, =LI (15) where Ix is balancing current for the two arms A+ and A-, I for arms B+ and B-, and Iz for arms C+ and C-, as outlined in Fig. 10.

One alternative solution for practical applications to the above constrained quadratic optimization problem in Eq. (14) is to add a penalizing term as oti/2112 (p r 0) to the unconstrained cost function of Eq. (14). This provides relaxation to the circulating current constraints that will result in minimizing circulating balancing current to as much as possible with a new cost function as follows: min.J2_ = (f12+ pI01-2+ LT (16) r.2 where /3 is an identity matrix of size 3 for three phase balancing application.

solution to the unconstrained quadratic optimization of balancing circulating currents as of Eq. (16) can be found using existing numerical constrained quadratic optimization methods.

Note that there are only 3 optimisation variable, Ix, /y, and lz, and hence optimization in real-time will be fine with available processing units.

Eq. (16) considers the fact that converter arm currents at the next designated step should include balancing currents that are to be calculated from Eq. (16). There are many methods of constrained or unconstrained QP numerical that can solve the optimization of Eq. (16) in real-time at low costs.

Please note that any other format of cost function penalizing such as reducing the effect of circulating current on dc link current by minimizing L2 norm of (lx+Iy-Flz)2 can also be fitted within the framework of Eq. (16). Thus, the dc link will not be affected due to MMC balancing. The above disclosed optimised MMC balancing current concept can be identically extended to other combination of circulating currents.

Fig. 10 illustrates the second embodiment of this disclosure based on Eq. (14) that includes a group of submodules that are connected in series in at least one arm (107,108,109,110,111,112). Two arms (one upper or positive, and one lower or negative arm) build a phase of MMC, that are connected between first and second DC terminals (VDc+, VDc.) that are separated by an AC terminal. Each positive (upper) converter arm of particular phase is connected to negative (lower) arm of the same phase via reactor L. The mathematical optimisation of Eq. (14) is embedded at (950). The inputs to (950) are all arms switching control positions (UA+, UA, UB+, Lk+, Lk), arm voltage outputs (VA+, VA, VB+, V8_, VC+, VC), and arm currents (IA+, la-, ils+, ic+, ic). The output of (950) is the solution to Eq. (14), that are optimum circulating currents for three phases of A, B and C. The optimization in Eq. (16) can be applied to various other cases, e.g. 6 independent circulating currents instead of three as disclosed above.

In all such cases, the concept of the cost function optimization is the same as disclosed in the flowchart as detailed in Method 1 in this disclosure.

Simulation Results MMC under normal operation: FIG 11 shows the typical simulation results of steady-state operation for a 20MW/20kV HB MMC with 15 submodules in each arm, including arm submodules instantaneous capacitor voltages (1103) and their average (1104). The aim is to minimize switching frequency to achieve average converter switching frequency around 60Hz while keeping all submodules capacitor voltages within their allowable limits of (1101-1102). FIG 12 shows the simulation results of the given arm reference voltage, Vref, (1201) and the actual converter arm voltage for arm A+, (1202). at normal operation. FIG 13 shows the simulation results of arm current (1301) and balancing current (1302) for arm A+, at normal operation. FIG 14 shows the simulation results of submodules frequency of arm A+ (1401) together with the average arm switching frequency (1402), at normal operation. This confirms that such minimal switching frequency could be achieved by submodule capacitors voltages ripples getting near to their limits; trying to get closer to submodules nominal voltages (i.e. getting away from min-max boundaries of the submodule capacitor voltage limits) will result in higher switching frequency; this is done automatically with mathematical optimisation disclosed herein. FIG 15 shows the controlled switching position (1501) and measured capacitor voltages of an individual submodule (1502) within arm A+, at normal operation.

MMC under abnormal (faulty) operation: FIG 16 shows the simulation results of three-phase to ground fault at time t=0.25 secs. The MMC is demanded to provide maximum reactive power to AC grid in supporting voltage. This is one of the requirements of converters in handling low voltage fault ride through (LVFRT) scenarios. This is the typical simulation results of operation for a 20MW/20kV HB MMC with 15 submodules in each arm, including arm submodules instantaneous capacitor voltages (1601) and their average (1602). It is intended to test the disclosed method for MMC switching control under faulty operation. The aim is to minimize switching frequency to achieve average converter switching frequency around 60Hz while keeping all submodules capacitor voltages within their allowable limits of (1101-1102) at the presence of three phase-to-ground fault at time t=0.5 secs. FIG 17 shows the simulation results of the given arm reference voltage, Vref, (1701) and the actual converter arm voltage for arm A+, (1702) at faulty operation, subject to three-phase to ground fault at time t=0.5 secs. FIG 18 shows the simulation results of dc current at dc side, subject to a fault at t=0.5 secs. As MMC is demanded to supply reactive power in the presense of fault, the dc current, after the fault at time t=0.5 sec, is not zero.

FIG 19 shows the simulation results of submodules frequency of arm A+ (1901) together with the average arm switching frequency (1902), at faulty operation. Note that the price for stabilising the MMC switching operation at such faulty condition will be paid by an increased switching frequency of submodules. This is expected as the disclosed mathematical optimisation will need to scarify some MMC performance, including increased arm average switching frequency, in order to guarantee stable MMC modulation with appropriate switching and maintaining balanced operation in the presence of faults that can violate the operation of converter.

Claims (25)

1. Claims 1. A method for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, using a modular multilevel converter comprising a plurality of submodules, each submodule configured to switch between at least two switching positions, and each submodule comprising at least one energy storage element, the method comprising: determining one or more changes to the switching position of each submodule to output the predetermined voltage, wherein said determination is based on at least one of: a switching history of each submodule, or collective group of neighbouring submodules, the location of each individual submodule from a reference point, the temperature of each submodule or the temperature of a collective group of neighbouring submodules, the voltage or energy output of each individual energy storage element, the health condition of each submodule, and the functionality of each submodule.
2. 2. The method of claim 1, wherein determining the changes to the switching position of each submodule to output the predetermined voltage is further based on minimising the total number of switching position changes of individual submodules over a set time period.
3. 3. The method of claims 1 or 2, wherein when the determination is based on the switching history of each submodule, the method further comprises the step of: updating a record of the number of times the switching position of each submodule has been changed.
4. 4. The method of any preceding claim, wherein the switching history of each submodule comprises a record of the number of times the position of each submodule has been changed over a set time period.
5. 5. The method of any preceding claim, further comprising receiving a current switching position for each submodule prior to determining the one or more changes to the switching position of each submodule to output the predetermined voltage.
6. 6. The method of any preceding claim, wherein the voltage or energy output of each individual storage element is the voltage or energy being released from each of the energy storage elements relative to the nominal voltage of each individual or average energy output of all the energy storage 30 elements.
7. 7. The method of any preceding claim, wherein the location of an individual submodule from the reference point is the height of the individual submodule from the reference point, and said height may be measured in distance, or in time taken by a worker to reach the individual submodule in order to replace the individual submodule completely or partly.
8. 8. The method of any preceding claim, wherein the frequency of changes to the switching position of each submodule, and the voltage across the energy storage elements, can be controlled independently and individually.
9. 9. The method of any previous claim, wherein the modular multilevel converter comprises one or more phase arms, each comprising the one or more submodules, and wherein the predetermined voltage is the predetermined voltage of the one or more phase arms, and determining the changes to the switching position of each submodule to output the predetermined voltage for the one or more phase arms comprises minimising a function of: the weighted sum of the number of changes to the switching position of each submodule; the weighted sum of the square of voltage ripple of each energy storage element, wherein voltage ripple is the voltage released or collected by an individual energy storage element relative to the nominal voltage of energy storage element, or the average voltage of the energy storage elements within a phase arm; and the weighted square of the output signal error, wherein the output signal error is the difference between the output signal and the predetermined voltage for the phase arm or their root mean square.
10. 10. The method of claim 9, wherein the sum of the number of changes of switching position of each submodule is weighted based on the number of times the switching position of each submodule has been changed, relative to the average amount of times a switching position of a submodule within the phase arm has been changed.
11. 11. The method of claims 9 or 10, wherein the function to be minimised is:
12. 12. The method of any of claims 9-11, wherein the submodules are half-bridge submodules with two switching positions, a first position and a second position; wherein the minimisation is performed by determining a solution to the minimisation of the function, the solution comprising a switching value for each submodule, wherein each switching value is non-quantized and therefore does not correspond directly to either position; thresholding the non-quantized switching values such that all values above a first threshold indicate the switching position is to be in the first position; thresholding the non-quantized switching values such that all values below the first threshold indicate the switching position is to be in the second position.
13. 13. The method of any of claims 9-11, wherein the submodules are full-bridge submodules with three switching positions, a first position, a second position and a third position; wherein the minimisation is performed by determining a solution to the minimisation of the function, the solution comprising a switching value for each submodule, wherein each switching value is non-quantized and therefore does not correspond directly to one of three positions; thresholding the non-quantized switching values such that all values above a first threshold indicate the switching position is to be in the first position; thresholding the non-quantized switching values such that all values below a second threshold indicate the switching position is to be in the second position; thresholding the non-quantized switching values such that all values below the first threshold, and above the second threshold indicate the switching position is to be in the third position.
14. 14. The method of claims 12 or 13, further comprising: determining the phase arm output voltage based on the solution to the function; comparing the determined phase arm output voltage to the predetermined voltage; determining if the determined phase arm output voltage and the predetermined voltage differ; in the event there is a difference changing switching values close to the threshold until the determined phase arm output voltage corresponds to the predetermined voltage, wherein changing the switching values starts by changing the switching value closest to the threshold, and continues until the predetermined voltage is achieved.
15. 15. The method of any of claims 9-14, wherein the weighted sum of the number of changes to the switching position of each submodule relative to the average number of times the switching position of all of the submodules have been changed is weighted according to at least one of the following parameters: a switching history of each individual submodule, the height of each individual submodule from a reference point, the health condition of each individual submodule or the health condition of a plurality of adjacent submodules, for example the temperatures of an individual submodule or a plurality of adjacent submodules, and the voltage or energy output of each individual energy storage element, whether a submodule is in a critical temperature range, the functionality of a submodule at different operating conditions, the proximity of a submodule to one or more submodules with a high number of switching position changes.
16. 16. The method of any preceding claim, wherein the switching frequency of an individual submodule, or average switching frequency of a plurality of submodules, is controllable to maintain the voltage of the energy storage elements within their allowed minimum and maximum voltage ranges during charging and discharging, during at both normal operation or abnormal operation if an internal or external fault is detected.
17. 17. A modular multilevel converter for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, the modular multilevel converter comprising a plurality of submodules, each submodule configured to have at least two switching positions, and each submodule comprising at least one energy storage element, and a controller, wherein the controller element is configured to perform the method of any of the above claims.
18. 18. The modular multilevel converter of claim 17, further comprising at least one or more phase units connected between a first terminal and a second terminal, wherein the phase units each comprise at least two phase arms, each separated by a third terminal; wherein each of the phase arms comprises two or more of the submodules connected in series.
19. 19. The modular multilevel converter of claim 17 or 18, wherein the energy storage element of each submodule is a direct current capacitor or a battery cell unit.
20. 20. The modular multilevel converter of claims 17-19, further comprising a thermistor configured to measure the temperature of each individual submodule or the temperature of a plurality of adjacent submodules.
21. 21. A modular multilevel converter for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage, the modular multilevel converter comprising one or more phase units connected between a first terminal and a second terminal, wherein the phase units each comprise two phase arms separated by a third terminal; wherein each of the arms comprises two or more of the submodules connected in series, each submodule configured to have at least two switching positions, and each submodule comprising at least one energy storage element; the modular multilevel converter configured to: monitor the output energy of each phase arm; calculate a balancing circulating current using a minimisation function; apply the balancing circulating current to at least one phase arm to balance the energy output of each phase arm, so that the switching frequency of submodules across each phase arm is equalised, and the number of changes to the switching position of submodules is minimised.
22. 22. A method of calculating optimum circulating currents for converting either alternating current to direct current, or direct current to alternating current, to create an output signal at a predetermined voltage for a phase arm, using a modular multilevel converter comprising one or more phase units connected between a first terminal and a second terminal, wherein the phase units each comprise two phase arms separated by a third terminal; wherein each of the arms comprises two or more of the submodules connected in series, each submodule configured to have at least two switching positions, and each submodule comprising at least one energy storage element, wherein the method comprises the steps of: monitoring the output energy of each phase arm; calculating a balancing circulating current using a minimisation function; applying the balancing circulating current to at least one phase arm to balance the energy output of each phase arm, so that the switching frequency of submodules across each phase arm is equalised, and the number of changes to the switching position of submodules is minimised.
23. 23. A system incorporating the modular multilevel converter of any of claims 18 to 22, wherein portions of the converter are held from a ceiling area of a structure such that they do not contact the ground; wherein converter is split into levels, each containing one or more of the submodules, and wherein a first level of submodules is closer to the ground than a second level of submodules, wherein the height of each submodule is used to determine the submodules to be switched to output the predetermined voltage.
24. 24. The system of claims 23, wherein the controller is configured to detect that at least one submodule will fail, and the controller is further configured to direct a submodule closer to the ground to fail instead of allowing a submodule further from the ground to fail, by controlling their individual or average switching frequency.
25. 25. A computer program product, or a tangible, non-transitory computer-readable medium configured to perform any of the method claims 1-17.