GB2585794A - Dual bootstrapping for an open-loop pulse width modulation driver - Google Patents

Dual bootstrapping for an open-loop pulse width modulation driver Download PDF

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Publication number
GB2585794A
GB2585794A GB2014612.2A GB202014612A GB2585794A GB 2585794 A GB2585794 A GB 2585794A GB 202014612 A GB202014612 A GB 202014612A GB 2585794 A GB2585794 A GB 2585794A
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GB
United Kingdom
Prior art keywords
effect transistor
type field
output
low
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB2014612.2A
Other versions
GB2585794B (en
GB202014612D0 (en
Inventor
Bai Jing
Das Tejasvi
Zhao Xin
Zhu Lei
Fei Xiaofan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic International Semiconductor Ltd
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Cirrus Logic International Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/162,960 external-priority patent/US11070203B2/en
Application filed by Cirrus Logic International Semiconductor Ltd filed Critical Cirrus Logic International Semiconductor Ltd
Publication of GB202014612D0 publication Critical patent/GB202014612D0/en
Publication of GB2585794A publication Critical patent/GB2585794A/en
Application granted granted Critical
Publication of GB2585794B publication Critical patent/GB2585794B/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/016—Input arrangements with force or tactile feedback as computer generated output to the user
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H04R3/12—Circuits for transducers, loudspeakers or microphones for distributing signals to two or more loudspeakers

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)

Abstract

A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

Claims (20)

WHAT IS CLAIMED IS:
1. A driver system comprising: a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated; a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated; a high-side capacitor coupled to the output of the driver system; and a low-side capacitor coupled to the second terminal of the supply voltage; wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.
2. The driver system of Claim 1, wherein the high-side capacitor further tracks a first offset occurring at a gate terminal of the first n-type field-effect transistor and corrects for the first offset at the output.
3. The driver system of Claim 2, wherein the low-side capacitor further tracks a second offset occurring at a gate terminal of the second n-type field-effect transistor and corrects for the second offset at the output.
4. The driver system of Claim 3, wherein the low-side capacitor further tracks the second offset in a manner that corrects for the first offset.
5. The driver system of Claim 1, wherein the tracking and correcting comprises controlling at least one of the first n-type field-effect transistor and the second n-type field-effect transistor during and after each edge transition of an output signal at the output.
6. The driver system of Claim 5, wherein the controlling comprises controlling the first resistance during a first edge transition of the output signal based on one of a voltage feedback through the gate of the first n-type field-effect transistor and a current feedback through the output.
7. The driver system of Claim 6, wherein the controlling comprises controlling the second resistance during a second edge transition of the output signal based on one of a voltage feedback through the gate of the second n-type field-effect transistor and the current feedback through the output.
8. The driver system of Claim 5, wherein the controlling after an edge transition controls at least one of the first resistance and the second resistance in order to correct for the mismatches between the first resistance and the second resistance.
9. The driver system of Claim 1, further comprising a dual-bootstrap subsystem configured to track and correct for mismatches between the first resistance and the second resistance, wherein the dual-bootstrap subsystem comprises: a high-side bootstrap switch coupled at its non-gate terminals between a second supply voltage and a high-side bootstrap capacitor such that the high-side bootstrap capacitor is coupled between the high-side bootstrap switch and the output; a high-side predriver configured to drive the gate of the first n-type field-effect transistor wherein respective power supply terminals of the high-side predriver are coupled to respective terminals of the high-side capacitor; a low-side bootstrap switch coupled at its non-gate terminals between the second supply voltage and a low-side bootstrap capacitor such that the low-side bootstrap capacitor is coupled between the low-side bootstrap switch and the second terminal of the supply voltage; and a low-side predriver configured to drive the gate of the second n-type field-effect transistor wherein respective power supply terminals of the low-side predriver are coupled to respective terminals of the low-side capacitor.
10. The driver system of Claim 9, wherein the supply voltage and the second supply voltage are a same voltage.
11. A method comprising, in a driver system comprising a first n-type field- effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage: tracking, by the high-side capacitor and the low-side capacitor, mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor; and correcting, by the high-side capacitor and the low-side capacitor, the mismatches.
12. The method of Claim 11, further comprising: tracking, by the high-side capacitor, a first offset occurring at a gate terminal of the first n-type field-effect transistor; and correcting, by the high-side capacitor, the first offset at the output.
13. The method of Claim 12, further comprising: tracking, by the low-side capacitor, a second offset occurring at a gate terminal of the second n-type field-effect transistor; and correcting, by the low-side capacitor, the second offset at the output.
14. The method of Claim 13, further comprising tracking, by the low-side capacitor, the second offset in a manner that corrects for the first offset
15. The method of Claim 11, wherein the tracking and correcting comprises controlling at least one of the first n-type field-effect transistor and the second n-type field-effect transistor during and after each edge transition of an output signal at the output
16. The method of Claim 15, wherein the controlling comprises controlling the first resistance during a first edge transition of the output signal based on one of a voltage feedback through the gate of the first n-type field-effect transistor and a current feedback through the output
17. The method of Claim 16, wherein the controlling comprises controlling the second resistance during a second edge transition of the output signal based on one of a voltage feedback through the gate of the second n-type field-effect transistor and the current feedback through the output .
18. The method of Claim 15, wherein the controlling after an edge transition controls at least one of the first resistance and the second resistance in order to correct for the mismatches between the first resistance and the second resistance.
19. The method of Claim 11, further comprising tracking and correcting for mismatches between the first resistance and the second resistance by a dual-bootstrap subsystem comprising: a high-side bootstrap switch coupled at its non-gate terminals between a second supply voltage and a high-side bootstrap capacitor such that the high-side bootstrap capacitor is coupled between the high-side bootstrap switch and the output; a high-side predriver configured to drive the gate of the first n-type field-effect transistor wherein respective power supply terminals of the high-side predriver are coupled to respective terminals of the high-side capacitor; a low-side bootstrap switch coupled at its non-gate terminals between the second supply voltage and a low-side bootstrap capacitor such that the low-side bootstrap capacitor is coupled between the low-side bootstrap switch and the second terminal of the supply voltage; and a low-side predriver configured to drive the gate of the second n-type field-effect transistor wherein respective power supply terminals of the low-side predriver are coupled to respective terminals of the low-side capacitor.
20. The method of Claim 19, wherein the supply voltage and the second supply voltage are the same voltage.
GB2014612.2A 2018-02-19 2019-01-30 Dual bootstrapping for an open-loop pulse width modulation driver Active GB2585794B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862632291P 2018-02-19 2018-02-19
US16/162,960 US11070203B2 (en) 2018-02-19 2018-10-17 Dual bootstrapping for an open-loop pulse width modulation driver
PCT/US2019/015795 WO2019160684A1 (en) 2018-02-19 2019-01-30 Dual bootstrapping for an open-loop pulse width modulation driver

Publications (3)

Publication Number Publication Date
GB202014612D0 GB202014612D0 (en) 2020-10-28
GB2585794A true GB2585794A (en) 2021-01-20
GB2585794B GB2585794B (en) 2022-04-20

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GBGB1901707.8A Ceased GB201901707D0 (en) 2018-02-19 2019-02-07 Dual bootstrapping for an open-loop pulse width modulation driver

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080252372A1 (en) * 2007-04-13 2008-10-16 Advanced Analogic Technologies, Inc. Power-MOSFETs with Improved Efficiency for Multi-channel Class-D Audio Amplifiers and Packaging Thereof
WO2011096175A1 (en) * 2010-02-08 2011-08-11 パナソニック株式会社 Digital amplifier
US20160028219A1 (en) * 2013-01-23 2016-01-28 Mitsubishi Electric Corporation Driving device for semiconductor elements, and semiconductor device
EP3136596A1 (en) * 2015-08-31 2017-03-01 Nxp B.V. A driver circuit for a power stage of a class-d amplifier

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008020386A1 (en) * 2006-08-16 2008-02-21 Nxp B.V. Power amplifier
US8310284B2 (en) * 2011-01-07 2012-11-13 National Semiconductor Corporation High-voltage gate driver that drives group III-N high electron mobility transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080252372A1 (en) * 2007-04-13 2008-10-16 Advanced Analogic Technologies, Inc. Power-MOSFETs with Improved Efficiency for Multi-channel Class-D Audio Amplifiers and Packaging Thereof
WO2011096175A1 (en) * 2010-02-08 2011-08-11 パナソニック株式会社 Digital amplifier
US20160028219A1 (en) * 2013-01-23 2016-01-28 Mitsubishi Electric Corporation Driving device for semiconductor elements, and semiconductor device
EP3136596A1 (en) * 2015-08-31 2017-03-01 Nxp B.V. A driver circuit for a power stage of a class-d amplifier

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YE ZICHAO ET AL, "A power supply circuit for gate driver of GaN-based flying capacitor multi-level converters", 2016 IEEE 4TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA), IEEE, (20161107), doi:10.1109/WIPDA.2016.7799909, pages 53 - 58 *

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Publication number Publication date
GB201901707D0 (en) 2019-03-27
GB2585794B (en) 2022-04-20
GB202014612D0 (en) 2020-10-28

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