GB2581945A - Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor - Google Patents

Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor Download PDF

Info

Publication number
GB2581945A
GB2581945A GB2009499.1A GB202009499A GB2581945A GB 2581945 A GB2581945 A GB 2581945A GB 202009499 A GB202009499 A GB 202009499A GB 2581945 A GB2581945 A GB 2581945A
Authority
GB
United Kingdom
Prior art keywords
instructions
instruction
dependency
issue queue
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB2009499.1A
Other versions
GB2581945B (en
GB202009499D0 (en
Inventor
Silberman Joel
Sinharoy Balaram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/826,746 external-priority patent/US10564976B2/en
Priority claimed from US15/826,734 external-priority patent/US10929140B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB202009499D0 publication Critical patent/GB202009499D0/en
Publication of GB2581945A publication Critical patent/GB2581945A/en
Application granted granted Critical
Publication of GB2581945B publication Critical patent/GB2581945B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)

Abstract

Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions. A dependency between the instruction and each of the other instructions is tracked. Instructions are issued from the issue queue based at least in part on the tracking.

Claims (31)

1. A computer-implemented method comprising: tracking dependencies between instructions in an issue queue, wherein the tracking comprises for each instruction in the issue queue: identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction, wherein a dependency between the instruction and each of the threshold number of instructions is tracked individually; and identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions, wherein a dependency between the instruction and each of the other instructions is tracked as one group or a plurality of groups by indicating that a dependency exists between the instruction and the one group or one of the plurality of groups based on identifying a dependency between the instruction and at least one of the other instructions or at least one instruction in the group of the plurality of groups, the one group of other instructions including all instructions in the issue queue that are not included in the threshold number of instructions that are tracked individually, and wherein each of the other instructions is assigned to at least one of the groups of the plurality of groups; and issuing instructions from the issue queue based at least in part on the tracking.
2. The computer-implemented method of claim 1 , comprising identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of a threshold number of instructions, wherein a dependency between the instruction and the other instructions is tracked as a single group by indicating that a dependency exists between the instruction and the single group of other instructions based on identifying a dependency between the instruction and at least one of the other instructions, the single group of other instructions including all instructions in the issue queue that are not included in the threshold number of instructions that are tracked individually.
3. The computer-implemented method of claim 1 , comprising identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions, wherein a dependency between the instruction and each of the other instructions is tracked as a plurality of groups by indicating that a dependency exists between the instruction and one of the groups based on identifying a dependency between the instruction and at least one instruction in the group, wherein each of the other instructions is assigned to at least one of the groups.
4. The computer-implemented method of claim 1 or claim 2, wherein the dependency between the instruction and the single group of other instructions is tracked using a single summary bit.
5. The computer-implemented method of claim 1 or claim 3, wherein dependencies between the instruction and each of the groups is tracked using a different summary bit for each of the groups.
6. The computer-implemented method of claim 4, wherein the single summary bit is set to indicate that a dependency exists between the instruction and at least one instruction in the single group of other instructions, and subsequent to the single summary bit being set, the single summary bit is reset to indicate that the dependency no longer exists between the instruction and the group of other instructions based at least in part on detecting that all of the other instructions in the single group of other instructions have been issued from the issue queue.
7. The computer-implemented method of claim 5, wherein the summary bit for each of the groups is set to indicate that a dependency exists between the instruction and at least one instruction in the group, and subsequent to the summary bit being set, the summary bit is reset to indicate that the dependency no longer exists between the instruction and the group based at least in part on detecting that all of the instructions assigned to the group have been issued from the issue queue.
8. The computer-implemented method of claim 1, wherein a dependency between the instruction and each of the threshold number of instructions is tracked using a separate bit for each of the threshold number of instructions.
9. The computer-implemented method of claim 1 , wherein the issue queue is a first-in-first-out (FIFO) queue and the instructions in the issue queue are ordered based on an order that they were added to the issue queue.
10. The computer-implemented method of claim 1 , wherein the instructions in the issue queue are from a single thread being executed by an out-of-order processor.
11. The computer-implemented method of claim 1 , wherein the issue queue holds N instructions and the threshold number of instructions is N/2.
12. The computer-implemented method of claim 1 , wherein the instructions in the each of the threshold number of instruction includes all of instructions in the issue queue that correspond to a single thread within a multi threading environment.
13. The computer-implemented method of claim 1 , wherein the threshold number is programmable.
14. A system comprising: a dependency matrix in an issue queue of an out-of-order processor; a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising: tracking dependencies between instructions in an issue queue, wherein the tracking comprises for each instruction in the issue queue: identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction, wherein a dependency between the instruction and each of the threshold number of instructions is tracked individually; and identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions, wherein a dependency between the instruction and each of the other instructions is tracked as one group or a plurality of groups by indicating that a dependency exists between the instruction and the one group or one of the plurality of groups based on identifying a dependency between the instruction and at least one of the other instructions or at least one instruction in the group of the plurality of groups, the one group of other instructions including all instructions in the issue queue that are not included in the threshold number of instructions that are tracked individually, and wherein each of the other instructions is assigned to at least one of the groups of the plurality of groups; and issuing instructions from the issue queue based at least in part on the tracking.
15. The system of claim 14, comprising identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of a threshold number of instructions, wherein a dependency between the instruction and the other instructions is tracked as a single group by indicating that a dependency exists between the instruction and the single group of other instructions based on identifying a dependency between the instruction and at least one of the other instructions, the single group of other instructions including all instructions in the issue queue that are not included in the threshold number of instructions that are tracked individually.
16. The computer-implemented method of claim 14, comprising identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions, wherein a dependency between the instruction and each of the other instructions is tracked as a plurality of groups by indicating that a dependency exists between the instruction and one of the groups based on identifying a dependency between the instruction and at least one instruction in the group, wherein each of the other instructions is assigned to at least one of the groups.
17. The system of claim 14 or claim 15, wherein the dependency between the instruction and the single group of other instructions is tracked using a single summary bit.
18. The system of claim 14 or claim 16, wherein dependencies between the instruction and each of the groups is tracked using a different summary bit for each of the groups.
19. The system of claim 17, wherein the single summary bit is set to indicate that a dependency exists between the instruction and at least one instruction in the single group of other instructions, and subsequent to the single summary bit being set the single summary bit is reset to indicate that the dependency no longer exists between the instruction and the group of other instructions based at least in part on detecting that all of the other instructions in the group of other instructions have been issued from the issue queue.
20. The system of claim 18, wherein the summary bit for each of the groups is set to indicate that a dependency exists between the instruction and at least one instruction in the group, and subsequent to the summary bit being set, the summary bit is reset to indicate that the dependency no longer exists between the instruction and the group based at least in part on detecting that all of the instructions assigned to the group have been issued from the issue queue.
21. The system of claim 14, wherein a dependency between the instruction and each of the threshold number of instructions is tracked using a separate bit for each of the threshold number of instructions.
22. The system of claim 14, wherein the issue queue is a first-in-first-out (FIFO) queue and the instructions in the issue queue are ordered based on an order that they were added to the issue queue.
23. The system of claim 14, wherein the instructions in the issue queue are from a single thread being executed by an out-of-order processor.
24. The system of claim 14, wherein the issue queue holds N instructions and the threshold number of instructions is N/2.
25. The system of claim 14, wherein the instructions in the each of the threshold number of instruction includes all of instructions in the issue queue that correspond to a single thread within a multi-threading environment.
26. The system of claim 14, wherein the threshold number is programmable.
27. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising: tracking dependencies between instructions in an issue queue, wherein the tracking comprises for each instruction in the issue queue: identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction, wherein a dependency between the instruction and each of the threshold number of instructions is tracked individually; and identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions, wherein a dependency between the instruction and each of the other instructions is tracked as one group or a plurality of groups by indicating that a dependency exists between the instruction and the one group or one of the plurality of groups based on identifying a dependency between the instruction and at least one of the other instructions or at least one instruction in the group of the plurality of groups, the one group of other instructions including all instructions in the issue queue that are not included in the threshold number of instructions that are tracked individually, and wherein each of the other instructions is assigned to at least one of the groups of the plurality of groups; and issuing instructions from the issue queue based at least in part on the tracking.
28. The computer program product of claim 27 comprising identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of a threshold number of instructions, wherein a dependency between the instruction and the other instructions is tracked as a single group by indicating that a dependency exists between the instruction and the single group of other instructions based on identifying a dependency between the instruction and at least one of the other instructions, the single group of other instructions including all instructions in the issue queue that are not included in the threshold number of instructions that are tracked individually.
29. The computer program product of claim 27, comprising identifying whether the instruction is dependent on one or more other instructions added to the issue queue prior to the instruction that are not included in the each of the threshold number of instructions, wherein a dependency between the instruction and each of the other instructions is tracked as a plurality of groups by indicating that a dependency exists between the instruction and one of the groups based on identifying a dependency between the instruction and at least one instruction in the group.
30. The computer program product of claim 27 or 28, wherein the dependency between the instruction and the single group of other instructions is tracked using a single summary bit; the single summary bit is set to indicate that a dependency exists between the instruction and at least one instruction in the single group of other instructions, and subsequent to the single summary bit being set, the single summary bit is reset to indicate that the dependency no longer exists between the instruction and the group of other instructions based at least in part on detecting that all of the other instructions in the single group of other instructions have been issued from the issue queue.
31. The computer program product of claim 27 or 29, wherein each of the other instructions is assigned to at least one of the groups, wherein dependencies between the instruction and each of the groups is tracked using a different summary bit for each of the groups; the summary bit for each of the groups is set to indicate that a dependency exists between the instruction and at least one instruction in the group; and subsequent to the summary bit being set, the summary bit is reset to indicate that the dependency no longer exists between the instruction and the group based at least in part on detecting that all of the instructions assigned to the group have been issued from the issue queue.
GB2009499.1A 2017-11-30 2018-11-09 Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor Active GB2581945B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/826,746 US10564976B2 (en) 2017-11-30 2017-11-30 Scalable dependency matrix with multiple summary bits in an out-of-order processor
US15/826,734 US10929140B2 (en) 2017-11-30 2017-11-30 Scalable dependency matrix with a single summary bit in an out-of-order processor
PCT/IB2018/058801 WO2019106462A1 (en) 2017-11-30 2018-11-09 Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor

Publications (3)

Publication Number Publication Date
GB202009499D0 GB202009499D0 (en) 2020-08-05
GB2581945A true GB2581945A (en) 2020-09-02
GB2581945B GB2581945B (en) 2021-01-20

Family

ID=66665478

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2009499.1A Active GB2581945B (en) 2017-11-30 2018-11-09 Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor

Country Status (5)

Country Link
JP (1) JP7403450B2 (en)
CN (1) CN111226196B (en)
DE (1) DE112018006103B4 (en)
GB (1) GB2581945B (en)
WO (1) WO2019106462A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114327643B (en) * 2022-03-11 2022-06-21 上海聪链信息科技有限公司 Machine instruction preprocessing method, electronic device and computer-readable storage medium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6463523B1 (en) * 1999-02-01 2002-10-08 Compaq Information Technologies Group, L.P. Method and apparatus for delaying the execution of dependent loads
CN101034345A (en) * 2007-04-16 2007-09-12 中国人民解放军国防科学技术大学 Control method for data stream and instruction stream in stream processor
CN102360309A (en) * 2011-09-29 2012-02-22 中国科学技术大学苏州研究院 Scheduling system and scheduling execution method of multi-core heterogeneous system on chip

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6988183B1 (en) * 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US7634591B2 (en) * 2006-01-26 2009-12-15 International Business Machines Corporation Method and apparatus for tracking command order dependencies
US8255671B2 (en) 2008-12-18 2012-08-28 Apple Inc. Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies
US8099582B2 (en) * 2009-03-24 2012-01-17 International Business Machines Corporation Tracking deallocated load instructions using a dependence matrix
WO2013077872A1 (en) * 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer and dependency reordering method
US10235180B2 (en) 2012-12-21 2019-03-19 Intel Corporation Scheduler implementing dependency matrix having restricted entries
JP6520416B2 (en) 2015-06-02 2019-05-29 富士通株式会社 Arithmetic processing apparatus and processing method of arithmetic processing apparatus
US10108417B2 (en) 2015-08-14 2018-10-23 Qualcomm Incorporated Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6463523B1 (en) * 1999-02-01 2002-10-08 Compaq Information Technologies Group, L.P. Method and apparatus for delaying the execution of dependent loads
CN101034345A (en) * 2007-04-16 2007-09-12 中国人民解放军国防科学技术大学 Control method for data stream and instruction stream in stream processor
CN102360309A (en) * 2011-09-29 2012-02-22 中国科学技术大学苏州研究院 Scheduling system and scheduling execution method of multi-core heterogeneous system on chip

Also Published As

Publication number Publication date
GB2581945B (en) 2021-01-20
GB202009499D0 (en) 2020-08-05
WO2019106462A1 (en) 2019-06-06
CN111226196B (en) 2023-12-01
JP7403450B2 (en) 2023-12-22
DE112018006103T5 (en) 2020-09-17
DE112018006103B4 (en) 2022-04-21
CN111226196A (en) 2020-06-02
JP2021504791A (en) 2021-02-15

Similar Documents

Publication Publication Date Title
US11003489B2 (en) Cause exception message broadcast between processing cores of a GPU in response to indication of exception event
US10831490B2 (en) Device and method for scheduling multiple thread groups on SIMD lanes upon divergence in a single thread group
US10049043B2 (en) Flushing control within a multi-threaded processor
WO2016183028A3 (en) Methods and architecture for enhanced computer performance
GB2581460A (en) Coalescing global completion table entries in an out-of-order processor
US10628351B2 (en) Sharing message-signaled interrupt vectors in multi-processor computer systems
WO2015153121A8 (en) A data processing apparatus and method for executing a stream of instructions out of order with respect to original program order
EP3091433A3 (en) System and method to reduce load-store collision penalty in speculative out of order engine
GB2581759A (en) Completing coalesced global completion table entries in an out-of-order processor
WO2007107707A3 (en) Computer architecture
JP2008515064A5 (en)
EP3258370A3 (en) Executing memory requests out of order
BR112018016913A2 (en) uniform predicates on shaders for graphics processing units
KR20100016347A (en) Thread de-emphasis instruction for multithreaded processor
WO2015017129A4 (en) Multi-threaded gpu pipeline
EP3140730A1 (en) Detecting data dependencies of instructions associated with threads in a simultaneous multithreading scheme
US9588770B2 (en) Dynamic rename based register reconfiguration of a vector register file
GB2579534A (en) Load-store unit with partitioned reorder queues with single cam port
GB2581945A (en) Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor
GB2540498A8 (en) Dynamic selection of memory management algorithm
US9753770B2 (en) Register-type-aware scheduling of virtual central processing units
RU2016134918A (en) PROCESSING LOGIC AND METHOD FOR DISPATCHING TEAMS FROM NUMEROUS THREADS
US20160004538A1 (en) Multiple issue instruction processing system and method
JP2016509306A5 (en)
US9311087B2 (en) Sticky bit update within a speculative execution processing environment

Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20210209