GB2579534A - Load-store unit with partitioned reorder queues with single cam port - Google Patents

Load-store unit with partitioned reorder queues with single cam port Download PDF

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Publication number
GB2579534A
GB2579534A GB2006338.4A GB202006338A GB2579534A GB 2579534 A GB2579534 A GB 2579534A GB 202006338 A GB202006338 A GB 202006338A GB 2579534 A GB2579534 A GB 2579534A
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United Kingdom
Prior art keywords
store
load
instruction
processing unit
partition
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GB2006338.4A
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GB202006338D0 (en
GB2579534B (en
Inventor
Sinharoy Balaram
Lloyd Bryan
Gonzales Christopher
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International Business Machines Corp
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International Business Machines Corp
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Priority claimed from US15/726,627 external-priority patent/US11175924B2/en
Priority claimed from US15/726,596 external-priority patent/US10606591B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB202006338D0 publication Critical patent/GB202006338D0/en
Publication of GB2579534A publication Critical patent/GB2579534A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.

Claims (20)

1. A processing unit for executing one or more instructions, the processing unit comprising: a load-store unit (LSU) configured to execute a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes by: selecting an instruction from the OoO window, the instruction using an effective address; and in response to the instruction being a load instruction: in response to the processing unit operating in a single thread mode, creating an entry in a first partition of a load reorder queue based on the instruction being issued on a first load pipe, and creating the entry in a second partition of the load reorder queue based on the instruction being issued on a second load pipe; and in response to the processing unit operating in a multi-thread mode where multiple threads are processed simultaneously, creating the entry in a first predetermined portion of the first partition of the load reorder queue based on the instruction being issued on the first load pipe and by a first thread of the processing unit.
2. The processing unit of claim 1, wherein in the multi-thread mode the first predetermined portion of the first partition of the load reorder queue is specific to load instructions issued by the first thread of the processing unit using the first load pipe.
3. The processing unit of claim 1 , the load-store unit further configured to: in response to the instruction being a store instruction: in response to the processing unit operating in the single thread mode, creating a store entry in a first partition of a store reorder queue based on the store instruction being issued on a first store pipe, and creating the store entry in a second partition of the store reorder queue based on the store instruction being issued on a second store pipe; and in response to the processing unit operating in the multi-thread mode, creating the store entry in a first predetermined portion of the first partition of the store reorder queue based on the store instruction being issued on the first store pipe and by the first thread of the processing unit.
4. The processing unit of claim 1 , wherein the load reorder queue comprises one partition for each load pipe of the LSU.
5. The processing unit of claim 4, wherein the LSU operates multiple load instructions concurrently, one load instruction using each respective load pipe.
6. The processing unit of claim 1 , wherein the store reorder queue comprises one partition for each store pipe of the LSU.
7. The processing unit of claim 6, wherein the LSU operates multiple store instructions concurrently, one store instruction using each respective load pipe.
8. A computer-implemented method for out-of-order execution of one or more instructions by a processing unit, the method comprising: receiving, by a load-store unit (LSU) of the processing unit, an out-of-order window of instructions comprising a plurality of instructions to be executed out-of-order; and issuing, by the LSU, instructions from the OoO window by: selecting an instruction from the OoO window, the instruction using an effective address; in response to the instruction being a load instruction: in response to the processing unit operating in a single thread mode, creating an entry in a first partition of a load reorder queue based on the instruction being issued on a first load pipe, and creating the entry in a second partition of the load reorder queue based on the instruction being issued on a second load pipe; and in response to the processing unit operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the load reorder queue based on the instruction being issued on the first load pipe and by a first thread of the processing unit.
9. The computer-implemented method of claim 8, wherein in the multi-thread mode the first predetermined portion of the first partition of the load reorder queue is specific to load instructions issued by the first thread of the processing unit using the first load pipe.
10. The computer-implemented method of claim 8, further comprising: in response to the instruction being a store instruction: in response to the processing unit operating in the single thread mode, creating a store entry in a first partition of a store reorder queue based on the store instruction being issued on a first store pipe, and creating the store entry in a second partition of the store reorder queue based on the store instruction being issued on a second store pipe; and in response to the processing unit operating in the multi-thread mode, creating the store entry in a first predetermined portion of the first partition of the store reorder queue based on the store instruction being issued on the first store pipe and by the first thread of the processing unit.
11. The computer-implemented method of claim 8, wherein the load reorder queue comprises one partition for each load pipe of the LSU.
12. The computer-implemented method of claim 11 , wherein the LSU operates multiple load instructions concurrently, one load instruction using each respective load pipe.
13. The computer-implemented method of claim 8, wherein the store reorder queue comprises one partition for each store pipe of the LSU.
14. The computer-implemented method of claim 13, wherein the LSU operates multiple store instructions concurrently, one store instruction using each respective load pipe.
15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing unit to cause the processing unit to perform operations comprising: receiving, by a load-store unit (LSU) of the processing unit, an out-of-order window of instructions comprising a plurality of instructions to be executed out-of-order; and issuing, by the LSU, instructions from the OoO window by: selecting an instruction from the OoO window, the instruction using an effective address; in response to the instruction being a load instruction: in response to the processing unit operating in a single thread mode, creating an entry in a first partition of a load reorder queue based on the instruction being issued on a first load pipe, and creating the entry in a second partition of the load reorder queue based on the instruction being issued on a second load pipe; and in response to the processing unit operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the load reorder queue based on the instruction being issued on the first load pipe and by a first thread of the processing unit.
16. The computer program product of claim 15, wherein in the multi-thread mode the first predetermined portion of the first partition of the load reorder queue is specific to load instructions issued by the first thread of the processing unit using the first load pipe.
17. The computer program product of claim 15, wherein in response to the instruction being a store instruction: in response to the processing unit operating in the single thread mode, creating a store entry in a first partition of a store reorder queue based on the store instruction being issued on a first store pipe, and creating the store entry in a second partition of the store reorder queue based on the store instruction being issued on a second store pipe; and in response to the processing unit operating in the multi-thread mode, creating the store entry in a first predetermined portion of the first partition of the store reorder queue based on the store instruction being issued on the first store pipe and by the first thread of the processing unit.
18. The computer program product of claim 15, wherein the load reorder queue comprises one partition for each load pipe of the LSU.
19. The computer program product of claim 18, wherein the LSU operates multiple load instructions concurrently, one load instruction using each respective load pipe.
20. The computer program product of claim 15, wherein the store reorder queue comprises one partition for each store pipe of the LSU, and wherein the LSU operates multiple store instructions concurrently, one store instruction using each respective load pipe.
GB2006338.4A 2017-10-06 2018-10-03 Load-store unit with partitioned reorder queues with single CAM port Active GB2579534B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US15/726,627 US11175924B2 (en) 2017-10-06 2017-10-06 Load-store unit with partitioned reorder queues with single cam port
US15/726,596 US10606591B2 (en) 2017-10-06 2017-10-06 Handling effective address synonyms in a load-store unit that operates without address translation
US15/825,494 US10606592B2 (en) 2017-10-06 2017-11-29 Handling effective address synonyms in a load-store unit that operates without address translation
US15/825,453 US11175925B2 (en) 2017-10-06 2017-11-29 Load-store unit with partitioned reorder queues with single cam port
PCT/IB2018/057695 WO2019069256A1 (en) 2017-10-06 2018-10-03 Load-store unit with partitioned reorder queues with single cam port

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GB202006338D0 GB202006338D0 (en) 2020-06-17
GB2579534A true GB2579534A (en) 2020-06-24
GB2579534B GB2579534B (en) 2020-12-16

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GB2006344.2A Active GB2579757B (en) 2017-10-06 2018-10-03 Handling effective address synonyms in a load-store unit that operates without address translation

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CN (2) CN111133413B (en)
DE (2) DE112018004004T5 (en)
GB (2) GB2579534B (en)
WO (2) WO2019069256A1 (en)

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JP2023056289A (en) 2021-10-07 2023-04-19 富士通株式会社 Arithmetic processing unit, and arithmetic processing method
CN114780146B (en) * 2022-06-17 2022-08-26 深流微智能科技(深圳)有限公司 Resource address query method, device and system

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CN111133421A (en) 2020-05-08
CN111133421B (en) 2023-09-29
GB2579757B (en) 2020-11-18
DE112018004004T5 (en) 2020-04-16
DE112018004006T5 (en) 2020-04-16
JP2020536308A (en) 2020-12-10
GB2579757A (en) 2020-07-01
CN111133413B (en) 2023-09-29
DE112018004006B4 (en) 2021-03-25
JP7064273B2 (en) 2022-05-10
CN111133413A (en) 2020-05-08
WO2019069256A1 (en) 2019-04-11
GB202006344D0 (en) 2020-06-17
GB202006338D0 (en) 2020-06-17
JP2020536310A (en) 2020-12-10
JP7025100B2 (en) 2022-02-24
WO2019069255A1 (en) 2019-04-11
GB2579534B (en) 2020-12-16

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