GB2579757B - Handling effective address synonyms in a load-store unit that operates without address translation - Google Patents

Handling effective address synonyms in a load-store unit that operates without address translation Download PDF

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Publication number
GB2579757B
GB2579757B GB2006344.2A GB202006344A GB2579757B GB 2579757 B GB2579757 B GB 2579757B GB 202006344 A GB202006344 A GB 202006344A GB 2579757 B GB2579757 B GB 2579757B
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GB
United Kingdom
Prior art keywords
operates
load
address
synonyms
store unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2006344.2A
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English (en)
Other versions
GB2579757A (en
GB202006344D0 (en
Inventor
Sinharoy Balaram
Lloyd Bryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/726,627 external-priority patent/US11175924B2/en
Priority claimed from US15/726,596 external-priority patent/US10606591B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB202006344D0 publication Critical patent/GB202006344D0/en
Publication of GB2579757A publication Critical patent/GB2579757A/en
Application granted granted Critical
Publication of GB2579757B publication Critical patent/GB2579757B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
GB2006344.2A 2017-10-06 2018-10-03 Handling effective address synonyms in a load-store unit that operates without address translation Active GB2579757B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US15/726,627 US11175924B2 (en) 2017-10-06 2017-10-06 Load-store unit with partitioned reorder queues with single cam port
US15/726,596 US10606591B2 (en) 2017-10-06 2017-10-06 Handling effective address synonyms in a load-store unit that operates without address translation
US15/825,494 US10606592B2 (en) 2017-10-06 2017-11-29 Handling effective address synonyms in a load-store unit that operates without address translation
US15/825,453 US11175925B2 (en) 2017-10-06 2017-11-29 Load-store unit with partitioned reorder queues with single cam port
PCT/IB2018/057694 WO2019069255A1 (en) 2017-10-06 2018-10-03 MANAGING EFFECTIVE ADDRESS SYNONYMS IN A LOADING-STORAGE UNIT OPERATING WITHOUT ADDRESS TRANSLATION

Publications (3)

Publication Number Publication Date
GB202006344D0 GB202006344D0 (en) 2020-06-17
GB2579757A GB2579757A (en) 2020-07-01
GB2579757B true GB2579757B (en) 2020-11-18

Family

ID=65994519

Family Applications (2)

Application Number Title Priority Date Filing Date
GB2006338.4A Active GB2579534B (en) 2017-10-06 2018-10-03 Load-store unit with partitioned reorder queues with single CAM port
GB2006344.2A Active GB2579757B (en) 2017-10-06 2018-10-03 Handling effective address synonyms in a load-store unit that operates without address translation

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB2006338.4A Active GB2579534B (en) 2017-10-06 2018-10-03 Load-store unit with partitioned reorder queues with single CAM port

Country Status (5)

Country Link
JP (2) JP7025100B2 (ja)
CN (2) CN111133413B (ja)
DE (2) DE112018004004T5 (ja)
GB (2) GB2579534B (ja)
WO (2) WO2019069256A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023056289A (ja) 2021-10-07 2023-04-19 富士通株式会社 演算処理装置および演算処理方法
CN114780146B (zh) * 2022-06-17 2022-08-26 深流微智能科技(深圳)有限公司 资源地址查询方法、装置、系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7343469B1 (en) * 2000-09-21 2008-03-11 Intel Corporation Remapping I/O device addresses into high memory using GART
CN103198028A (zh) * 2013-03-18 2013-07-10 华为技术有限公司 一种内存数据迁移方法、装置及系统
WO2016105961A1 (en) * 2014-12-26 2016-06-30 Wisconsin Alumni Research Foundation Cache accessed using virtual addresses
US9740409B2 (en) * 2013-12-13 2017-08-22 Ineda Systems, Inc. Virtualized storage systems

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694425B1 (en) 2000-05-04 2004-02-17 International Business Machines Corporation Selective flush of shared and other pipeline stages in a multithread processor
US6931639B1 (en) * 2000-08-24 2005-08-16 International Business Machines Corporation Method for implementing a variable-partitioned queue for simultaneous multithreaded processors
US20040117587A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Hardware managed virtual-to-physical address translation mechanism
US7730282B2 (en) * 2004-08-11 2010-06-01 International Business Machines Corporation Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US8145887B2 (en) * 2007-06-15 2012-03-27 International Business Machines Corporation Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor
US8645974B2 (en) * 2007-08-02 2014-02-04 International Business Machines Corporation Multiple partition adjunct instances interfacing multiple logical partitions to a self-virtualizing input/output device
US7711929B2 (en) * 2007-08-30 2010-05-04 International Business Machines Corporation Method and system for tracking instruction dependency in an out-of-order processor
US8639884B2 (en) * 2011-02-28 2014-01-28 Freescale Semiconductor, Inc. Systems and methods for configuring load/store execution units
US9182991B2 (en) * 2012-02-06 2015-11-10 International Business Machines Corporation Multi-threaded processor instruction balancing through instruction uncertainty
US8966232B2 (en) * 2012-02-10 2015-02-24 Freescale Semiconductor, Inc. Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
GB2503438A (en) * 2012-06-26 2014-01-01 Ibm Method and system for pipelining out of order instructions by combining short latency instructions to match long latency instructions
US10209995B2 (en) * 2014-10-24 2019-02-19 International Business Machines Corporation Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7343469B1 (en) * 2000-09-21 2008-03-11 Intel Corporation Remapping I/O device addresses into high memory using GART
CN103198028A (zh) * 2013-03-18 2013-07-10 华为技术有限公司 一种内存数据迁移方法、装置及系统
US9740409B2 (en) * 2013-12-13 2017-08-22 Ineda Systems, Inc. Virtualized storage systems
WO2016105961A1 (en) * 2014-12-26 2016-06-30 Wisconsin Alumni Research Foundation Cache accessed using virtual addresses

Also Published As

Publication number Publication date
CN111133421A (zh) 2020-05-08
CN111133421B (zh) 2023-09-29
DE112018004004T5 (de) 2020-04-16
DE112018004006T5 (de) 2020-04-16
JP2020536308A (ja) 2020-12-10
GB2579757A (en) 2020-07-01
CN111133413B (zh) 2023-09-29
DE112018004006B4 (de) 2021-03-25
JP7064273B2 (ja) 2022-05-10
CN111133413A (zh) 2020-05-08
WO2019069256A1 (en) 2019-04-11
GB202006344D0 (en) 2020-06-17
GB202006338D0 (en) 2020-06-17
JP2020536310A (ja) 2020-12-10
JP7025100B2 (ja) 2022-02-24
WO2019069255A1 (en) 2019-04-11
GB2579534A (en) 2020-06-24
GB2579534B (en) 2020-12-16

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Effective date: 20201201