GB2557911A

GB2557911A - Circuit arrangement

Info

Publication number: GB2557911A
Application number: GB1621366.2A
Authority: GB
Inventors: Dominik Moczek Aleksander
Original assignee: A Tech Fabrications Ltd
Current assignee: A Tech Fabrications Ltd
Priority date: 2016-12-15
Filing date: 2016-12-15
Publication date: 2018-07-04
Anticipated expiration: 2036-12-15
Also published as: GB201621366D0; GB2557911B

Abstract

A circuit arrangement for converting an input signal generated by a sensor to a logic output comprises a voltage divider 102 connected between a supply potential +V and ground and having first 105 and second 106 resistive loads in series; a sensor input line 107 connected between the first and second resistive loads; a first buffer circuit 103 having an input connected to the voltage divider between the sensor input line and the supply potential; and a second buffer circuit 104, whose input is connected to the voltage divider between the sensor input line and the ground connection. Each buffer circuit comprises a feedback resistive load 111,112 connected between its input and output and can be a non-inverting buffer or two inverting buffers (fig 4, 403,404,) in series and the first buffer circuit can include an inverter 114. The buffers can provide hysteresis and immunity from noise (fig 2) for a sensor such as a Hall effect sensor whose zero-point is half the supply potential +V, the separation between input switching voltages being set by the feedback resistor and the level of switching voltage being set by a respective potentiometer 108,109 in series with the potential divider. Inputs to the buffers can be coupled to ground by capacitors 117.

Description

(54) Title ofthe Invention: Circuit arrangement

Abstract Title: Circuit for converting a sensor input to a logic output (57) A circuit arrangement for converting an input signal generated by a sensor to a logic output comprises a voltage divider 102 connected between a supply potential +V and ground and having first 105 and second 106 resistive loads in series; a sensor input line 107 connected between the first and second resistive loads; a first buffer circuit 103 having an input connected to the voltage divider between the sensor input line and the supply potential; and a second buffer circuit 104, whose input is connected to the voltage divider between the sensor input line and the ground connection. Each buffer circuit comprises a feedback resistive load 111,112 connected between its input and output and can be a non-inverting buffer or two inverting buffers (fig 4, 403,404,) in series and the first buffer circuit can include an inverter 114. The buffers can provide hysteresis and immunity from noise (fig 2) for a sensor such as a Hall effect sensor whose zero-point is half the supply potential +V, the separation between input switching voltages being set by the feedback resistor and the level of switching voltage being set by a respective potentiometer 108,109 in series with the potential divider. Inputs to the buffers can be coupled to ground by capacitors 117.

Figi

1/4

101

Figi

2/4 (i)

3/4

301

O/Pj

O/P₂

Fig 3

4/4

Fig 4

Circuit Arrangement

Technical Field

The present invention relates to circuit arrangements for converting an input signal generated by a sensor to a logical output.

Background

Output signals from sensors typically include a noise component. For example, a typical Hall Effect sensor is arranged to generate an output signal which varies depending on the polarity of a magnetic field detected by the sensor. Even in ideal conditions, the output signal of such a sensor may include a significant noise component, but if the environment in which the sensor is operating is likely to contain significant noise sources, then the output signal from the sensor might become unusable.

For example, in certain scenarios, a vehicle, such as an autonomous guided vehicle (AGV), is arranged to follow a magnetised metallic guidance strip to enable the vehicle to move around a location without being controlled by a human operator. The vehicle includes a magnetic sensor including an array of Hall Effect sensors arranged to detect the metallic strip and from this generate movement (steering and speed) controls. In certain circumstances, the metallic guidance track may further include additional control sections of metallic strip on which control information is encoded. The control information provides instructions for the AGV to perform certain actions such as a forklift pick up or forklift set down operation. The control information is encoded by differently magnetising (e.g. north polarity or south polarity) specific blocks of the control sections. The magnetic sensor of the AGV is arranged to read such control sections by the array of Hall Effect sensors detecting the polarity of the blocks as the magnetic sensor array moves over them.

In order to correctly read the control sections, the magnetic sensor array must accurately detect the polarity of the magnetic field of each specific block. In an environment in which there may be metallic objects nearby (e.g. ferrous nuts and bolts dropped on the floor) and sources of electromagnetic noise (e.g. emanating from welding equipment), then operation of the Hall Effect sensors may be compromised as the levels of “magnetic noise” will be high.

It is desirable to provide a circuit arrangement which can convert a sensor signal generated by a sensor, such as a Hall Effect sensor operating in the type of scenario described above, into a logical output even in conditions where there is a high level of noise present in the sensor signal.

Summary of the Invention

In accordance with a first aspect of the invention there is provided a circuit arrangement for converting an input signal generated by a sensor to a logic output, said circuit arrangement comprising: a voltage divider between a supply potential and a ground connection comprising first and second resistive load connected in series; a sensor input line connected between the first and second resistive load, and first and second buffer circuits, an input of the first buffer circuit connected to the voltage divider between the sensor input line and the supply potential, and an input of the second buffer circuit connected to the voltage divider between the sensor input line and the ground connection. Each buffer circuit comprises a buffer and a feedback resistive load connecting an output of the buffer to the input of the buffer.

Optionally, the buffer of each buffer circuit is provided by a non-inverting buffer.

Optionally, the first buffer circuit further comprises an inverter connected to an output of the non-inverting buffer.

Optionally, the buffer of each buffer circuit is provided by two inverting buffers in series.

Optionally, an output of the first buffer circuit goes high if an input voltage on the sensor input line drops below a first voltage level and goes low if the input voltage on the sensor input line subsequently rises above a second voltage level, and an output of the second buffer circuit goes high if an input voltage on the sensor input line rises above a third voltage level, and goes low if the input voltage on the sensor input lines subsequently drops below a fourth voltage level.

Optionally, the second voltage level is above the first voltage level, and the third voltage level is above the fourth voltage level.

Optionally, the first voltage level is below the fourth voltage level and the third voltage level is above the second voltage level.

Optionally, a value of the feedback resistive load of the first buffer circuit determines a voltage separation between the first voltage level and the second voltage level, and a value of the feedback resistive load of the first buffer circuit determines a voltage separation between the third voltage level and the fourth voltage level.

Optionally, the first resistive load comprises a first resistor and first potentiometer in series and the input of the first buffer circuit is connected to the voltage divider via the first potentiometer.

Optionally, a value set on the first potentiometer determines a voltage level of the first voltage and the second voltage level.

Optionally, the second resistive load comprises a second resistor and second potentiometer in series and the input of the second buffer circuit is connected to the voltage divider via the second potentiometer.

Optionally, a value set on the second potentiometer determines a voltage level of the third voltage and the fourth voltage level.

Optionally, the input of the first and second buffer circuits are capacitively coupled to ground by a capacitive coupling.

Optionally, a zero-point of the input signal from the sensor is substantially half the supply potential.

According to a second aspect of the invention, there is provided a sensor system comprising a sensor coupled to a circuit arrangement in accordance with the first aspect of the invention.

Optionally, the sensor is a Hall Effect sensor.

In accordance with certain aspects of the invention an improved circuit arrangement is provided which advantageously can convert a noisy input signal generated by a sensor, into an logic output signal. In particular, the circuit arrangement can generate a logic output signal even in certain circumstances where the amplitude of the noise is greater than the amplitude of the sensor signal.

Advantageously, in certain embodiments the response of the circuit arrangement can be readily configured by controlling the values of the first and second potentiometers and the value of the first and second feedback resistors.

Advantageously, in certain embodiments, the buffers of the buffer circuits can be provided by a single integrated circuit allowing convenient construction of the circuit arrangement.

Advantageously, in certain embodiments, the capacitive value of the capacitive coupling can be adjusted to determine frequencies which are filtered from the sensor input.

Various aspects and features of the invention are defined in the claims.

Brief Description of Figures

Certain embodiments of the present invention will now be described hereinafter, by way of example only, with reference to the accompanying drawings in which:

Figure 1 provides a schematic diagram of a circuit arrangement in accordance with certain embodiments of the invention;

Figure 2 provides a number of graphs depicting the operation of circuit arrangements in accordance with certain examples of the invention;

Figure 3 provides a schematic diagram showing a sensor system in which circuit arrangements in accordance with examples of the invention can be used, and

Figure 4 provides a schematic diagram of a circuit arrangement in accordance with certain embodiments of the invention.

In the drawings like reference numerals refer to like parts.

Detailed Description

Figure 1 provides a schematic diagram of a circuit arrangement 101 in accordance with certain examples of the invention.

The circuit arrangement 101 includes a voltage divider 102 between a supply voltage (+V) and a ground connection. Coupled to the voltage divider 102 is a first buffer circuit 103 and a second buffer circuit 104.

The voltage divider 102 includes a first resistor 105 connected directly to the supply voltage and a second resistor 106 connected directly to the ground connection.

A sensor input line 107 is connected to the voltage divider 102 at its midpoint. The sensor input line 107 includes a sensor input line resistor 118. The first buffer circuit 103 is connected to the voltage divider 102 via a first potentiometer 108 which is connected in series with the first resistor 105. The second buffer circuit 104 is connected to the voltage divider 102 via a second potentiometer 109 which is connected in series with the second resistor 106. The sensor input line 107 is connected to the voltage divider 102 between the first potentiometer 108 and the second potentiometer 109.

The first buffer circuit 103 comprises a first buffer 110 and a feedback resistor 111. The feedback resistor 111 is connected between the input and output of the first buffer 110. An inverter 114 is connected to the output of the first buffer 110 after the input of the feedback resistor 111 and the output of the inverter 114 forms the output of the first buffer circuit 103.

The second buffer circuit 104 comprises a second buffer 112 and a second feedback resistor 113. The second feedback resistor 113 is connected between the input and output of the second buffer 112.

The circuit arrangement 101 has a first output 115 which is the output of the first buffer circuit 103 (the output of the inverter 114) and a second output 116 which is the output of the second buffer circuit 104 (the output of the second buffer).

In the example shown in Figure 1, the first buffer 110 and second buffer 112 are provided by a single non-inverting buffer which is a logic component well-known in the art.

The input of both the first buffer circuit 103 and the second buffer circuit 104 are capacitively coupled to ground via a capacitive coupling 117.

In certain embodiments, typical values for the first and second feedback resistors 111, 112 are around 220kO - 1.2ΜΩ. Typical values of the first and second resistors 105, 106 are around 22kQ. Typical values for the first and second potentiometers 108, 109 are around 410Ω - 820Ω. The potentiometers may be set at around 470Ω. Typical values of the capacitors of the capacitive coupling 117 are between around 10pF and around 470nF. The buffers of the buffer circuits can be provided by any suitable means. In some examples, the buffers are provided by a suitable integrated circuit (1C) such as a 4050 series 1C such as a 54HC4050; 54HC4050RPFB; 54HC4050RPFE; 54HC4050RPFI; or 54HC4050RPFS from Maxwell Technologies.

In operation, the voltage level at the sensor input line 107 varies in accordance with output of the sensor. For optimal operation of the circuit arrangement, the “zero-point” - i.e. no measurement detected of the sensor is arranged to be half the supply voltage, that is half the value of +V (i.e. V/2) shown in Figure 1. If the sensor output is at the zero-point (V/2), the output of the first buffer 110 is low and the output of the second buffer 112 is high. Accordingly, the output of the first buffer circuit 103 is zero (because the output of the first buffer 110 is inverted by the inverter 114) and the output of the second buffer circuit 104 is low.

More specifically, in the event that the sensor output is at the zero-point, i.e. the voltage on the sensor input line 107 is V/2, the values of the resistors 105 and 106, and the settings of the potentiometers 108 and 109 are such that the voltage level at point (e) shown in Figure 1 is below a threshold voltage V_ei required to turn on the second buffer 112. Further, the values of the resistors 105 and 106, and the settings of the potentiometers 108 and 109 are such that the voltage level at point (d) shown in Figure 1 is above a threshold voltage V_di required to turn off the first buffer 110.

In the event that the sensor output rises above the zero-point i.e. the voltage on the sensor input line 107 is greater than V/2, the voltage level at point (e) shown in Figure 1 begins to rise.

Once the voltage on the sensor input line 107 has risen above a threshold level for a period of time determined by the value of the capacitive coupling 117, the voltage level at point (e) exceeds V_ei, and the second buffer 112 switches on.

Once the buffer 112 has switched on, the effect of the feedback resistor 113 is such that the voltage level at point (e) must, for a period of time defined by the value of the capacitive coupling 117, fall below a second threshold voltage V_e2, lower than V_ei for the second buffer 112 to switch off again.

In the event that the sensor output drops below the zero-point i.e. the voltage on the sensor input line 107 is greater than V/2, the voltage level at point (d) shown in Figure 1 begins to drop.

Once the voltage on the sensor input line 107 has dropped below a threshold level for a period of time determined by the value of the capacitive coupling 117, the voltage level at point (d) drops below V_di and the first buffer 110 switches off. Because of the inverter 114, the output of the first buffer circuit 103 goes high.

Once the first buffer 110 has switched off, because of the effect of the feedback resistor 111, the voltage level at point (d) must, for the predetermined period of time determined by the value of the capacitive coupling 117, rise above a second threshold voltage V_d2, which is higher than V_ei for the first buffer 112 to switch on again. When the voltage level at point (d) rises above V_d2 for the predetermined period of time, the first buffer 110 switches on and, due to the inverter 114, the output of the first buffer unit goes low again.

It will be understood with reference to Figure 1 that the effect of the feedback from the output of the first and second buffers 110, 112 to their respective inputs depends on the value of the resistors 105, 106 of the voltage divider and the positions at which the potentiometers 108, 109 are set. The higher the resistances on the voltage divider, the higher the effect of the feedback.

The circuit arrangement 101 shown in Figure 1 with the typical component values detailed above is arranged such that, within operational limits, a signal from a sensor with a noise component which is of greater magnitude than the sensor signal itself can be converted into a logical output indicative of the sensor signal. This is explained further with reference to the graphs depicted in Figure 2.

The first graph (i) of Figure 2 models an output signal from a Hall Effect sensor generated without a noise component and as if the Hall Effect sensor was periodically detecting a magnetic field with a north polarity followed by a magnetic field with a south polarity followed by a magnetic field with a north polarity and so on. This models an output that might be expected from a Hall Effect sensor passing over a metallic strip with alternately magnetised sections, that is a section magnetised with a north polarity followed by a section magnetised with a south polarity followed by a section magnetised with a north polarity and so on.

In the modelled output signal shown in the first graph (i) a first voltage level V_s corresponds to a Hall Effect sensor detecting a magnetic field with a south polarity. This voltage level models a Hall Effect sensor being directly above a section of metallic strip magnetised with a south polarity. A second voltage level V_n corresponds to a Hall Effect sensor detecting a magnetic field with a south polarity. This voltage level models a Hall Effect sensor being directly above a section of metallic strip magnetised with a north polarity. A third voltage level, V/2 models no magnetic field with a specific polarity detected. This voltage level models a Hall Effect sensor being directly between a section of metallic strip magnetised with a north polarity and a section of metallic strip magnetised with a south polarity. The third voltage level V/2 is the zero point voltage and is arranged to match half the supply voltage of the circuit arrangement.

As can be seen from the first graph, to more clearly demonstrate the operation of the circuit arrangement, the output signal from the Hall Effect sensor is modelled as a triangle wave. As mentioned above, the modelled signal shown in the first graph (i) does not include a noise component.

The second graph (ii) in Figure 2 corresponds to the modelled sensor signal output shown in the first graph (i), except that the sensor signal input includes noise component. As can be seen from the second graph, the dynamic range of the noise is greater than the dynamic range of the signal itself.

The circuit arrangement 101 shown in Figure 1 is arranged to convert the type of sensor signal shown in the second graph (ii) of Figure 2 into a logical output corresponding to the signal shown in the top graph of Figure 2. More specifically, the circuit arrangement is arranged to output a logical high on a first output when a magnetic field with a south polarity is detected and a logical high on a second output when a magnetic field with a north polarity is detected. When neither is detected, both first and second outputs are low.

The third graph (iii) and the fourth graph (iv) shown in Figure 2 show the modelled output of the circuit arrangement 101 when the sensor signal shown in second graph (ii) is input on the sensor input line 107. More specifically, the third graph (iii) shows the output of the first buffer circuit 103 and the fourth graph (iv) shows the output of the second buffer circuit 104.

Specifically, in accordance with the operation of the circuit arrangement explained with reference to Figure 1 above, if the sensor signal shown in the second graph (ii) drops below a first voltage level (Ο/Pi on) then the output of the first buffer circuit 103 goes high. The first voltage level (Ο/Pi on) is lower than half the supply voltage level V/2. The voltage levels (O/Pi on; Ο/Pi off) are shown the second graph (ii) and, as mentioned above, the output of the first buffer circuit 103 is shown in the third graph (iii) of Figure 2. As can be seen, these voltage level conditions are met during a second (T₂), sixth (T₆) and tenth (T_w) time period. Thus, during these time periods, the output of the first buffer circuit 103 is high indicating a magnetic field with a north polarity has been detected. Subsequently, the output of the first buffer circuit 103 will only go low if the sensor signal rises above a second voltage level (Ο/Pi off) for a predetermined period of time determined by the capacitive value of the capacitive coupling.

Further, in the event that the sensor signal rises above a third voltage level (O/P₂ on) then the output of the second buffer circuit 104 goes high. The third voltage level (O/P₂ on) is greater than half the supply voltage level v/2. The voltage levels (O/P₂ on; O/P₂ off) are shown the second graph (ii) and the output of the second buffer circuit 104 is shown in the fourth graph (iv) on Figure 2. As can be seen from Figure 2, the voltage level conditions described above are met during time a fourth (T₄), eighth (T₈) and twelfth (Τ_Ί2) time period. Thus, during these time periods, the output of the second buffer circuit 104 is high indicating a magnetic field with a south polarity has been detected. Subsequently, the output of the second buffer circuit 104 will only go low if the sensor signal drops below a fourth voltage level (O/P₂ off) determined by the capacitive value of the capacitive coupling.

As can be seen from the third and fourth graph, in the event that the signal falls past the fourth voltage level (O/P₂ off) but not as far as the first voltage level (Ο/Pi on) and the signal rises past the second voltage level (Ο/Pi off) but not as far as the third voltage level (O/P₂ on), then the outputs of both buffer circuits remain low.

As will be understood, by setting the voltage levels (O/P₂ on), (Ο/Pi off), (O/P₂ off) and (O/Pi on) as shown on the second graph (ii) the circuit arrangement is able to generate the logical output signals shown in the third (iii) and fourth (iv) graphs whilst tolerating noise levels that are of a greater dynamic range than the actual sensor signal.

The circuit arrangement is such that the first voltage level (Ο/Pi on) is at voltage level below the fourth voltage level (O/P₂ off) and the third voltage level (O/P₂ on) is above the second voltage level 0/P₂off. In this way it is ensured that only one of the first buffer circuit 103 and the second buffer circuit 102 is ever high. A fifth graph (v) is shown in Figure 2 which shows how the voltage level over time at point c) of the circuit arrangement varies as the input signal shown in the second graph (ii) varies.

The fifth graph (v) and the sixth graph (vi) show how during the fourth (T₂), sixth (T₆), and tenth (Tw) time period, the effect of the feedback resistor of the first buffer circuit “pulls down” the voltage at point (c) of the circuit arrangement, and during the fourth (T₄), sixth (T₆), and twelfth (Ti₂) time period, the effect of the feedback resistor of the second buffer circuit “pulls up” the voltage at point (c) of the circuit arrangement. Correspondingly, a sixth graph (vi) is shown in Figure 2 which shows how the voltage level over time at point d) of the circuit arrangement and point e) of the circuit arrangement varies as the input signal shown in the second graph (ii) varies.

As can be seen from the second graph (ii) of Figure 2, the descending order of the voltage levels is the third voltage level (O/P₂ on), the second voltage level (O/P1 off), the fourth voltage level (O/P₂ off), and the first voltage level (O/P1 on).

In operation, the resistive value of the first feedback resistor 111 determines the width of the voltage separation between the second voltage level (O/P1 off) and the first voltage level (O/P1 on). The greater the resistive value of the first feedback resistor 111, the greater the width of this voltage separation.

Further, in operation, the value set on the first potentiometer 108 determines the absolute position of the second voltage level (O/P1 off) and the first voltage level (O/P1 on) the vertical axis shown in the bottom graph on Figure 2. In other words, the value set on the first potentiometer 108 determines the actual voltage level of the second voltage level (O/P1 off) and the first voltage level (O/P1 on). For example, if the value set on the first potentiometer 108 is increased by a certain amount then the voltage level of both the second voltage level (O/P1 off) and the first voltage level (O/P1 on) increases by a corresponding amount. Accordingly, increasing the value set on the first potentiometer 108 increases the sensitivity of the first buffer circuit 103.

Further, in operation, the resistive value of the second feedback resistor 113 determines the width of the voltage separation between the fourth voltage level (O/P₂ off) and the third voltage level (O/P₂ on). The greater the resistive value of the second feedback resistor 113, the greater the width of the voltage separation.

Further, in operation, the value set on the first potentiometer 109 determines the absolute position of the fourth voltage level (O/P₂ off) and the third voltage level (O/P₂ on) on the vertical axis shown in the bottom graph on Figure 2. In other words, the value set on the second potentiometer 109 determines the actual voltage level of the fourth voltage level (O/P₂ off) and the third voltage level (O/P₂ on). For example, if the value set on the second potentiometer

109 is increased by a certain amount then the voltage level of both the fourth voltage level (O/P₂ off) and the third voltage level (O/P₂ on) reduces by a corresponding amount. Accordingly, decreasing the value set on the second potentiometer 109 increases the sensitivity of the second buffer circuit 103.

As will be understood therefore, advantageously, in certain embodiments, the response of the circuit arrangement to various input signals can be readily configured by controlling the values of the first and second potentiometers and the value of the first and second feedback resistors.

In operation, the capacitive coupling 117 that capacitively couples the input of both the first buffer circuit 103 and the second buffer circuit 104 to ground is arranged to filter out sensor signals above a certain frequency. For example, the values of the capacitors of which the capacitive coupling 117 comprises can be selected to ensure that only signals below 800Hz are passed to the first and second buffer circuits.

As mentioned above, increasing the value set on the first potentiometer 108 increases the sensitivity of the first buffer circuit 103 and decreasing the value set on the second potentiometer 109 increases the sensitivity of the second buffer circuit 103. Typically, the values set on the first and second potentiometers will be the same so that the circuit arrangement is equally sensitive to noise on parts of the input sensor signal that are above the zero point and parts of the input sensor signal that are below the zero point. However, if circumstances are such that the input sensor signal includes more noise on one side of the zero point, then the values set on the first and second potentiometer can be set differently to accommodate this.

In the example explained with reference to Figure 2, the values of the first and second feedback resistors 111, 113 and the value of the first and second potentiometers 108, 109 are set so that the descending order of the voltage levels is the third voltage level (O/P₂ on), the second voltage level (Ο/Pi off), the fourth voltage level (O/P₂ off), and the first voltage level (Ο/Pi on). As will be understood, this ensures that only one buffer circuit will ever give a high output but means that the input signal only needs to change a small amount from one buffer circuit going to low to the other buffer circuit going high. However, in other examples, the voltage levels first, second, third and fourth voltage levels can be set so that the input sensor signal needs to change by a greater amount before one buffer circuit goes high after the other goes low. This can be achieved by swapping the position of the second voltage level (O/Pi off) and the fourth voltage level (O/P₂ off), so that the descending order of the voltage levels is the third voltage level (0/P₂ on), the fourth voltage level (O/P₂ off), the second voltage level (Ο/Pi off), and the first voltage level (Ο/Pi on).

In certain examples, the second voltage level (O/P1 off) and the fourth voltage level (O/P₂ off) can be set at the same level, for example half the supply voltage V/2.

Figure 3 provides a schematic diagram of a sensor system 301 in which the circuit arrangement depicted in Figure 1 can be implemented.

The system includes a supply rail 302 and a ground connection 303. A Hall Effect sensor 304 is connected to the supply rail 302 and an output of the Hall Effect sensor 304 is input to a temperature stabiliser circuit 305 which stabilises the output of the Hall Effect sensor 304 to accommodate for sensor signal variance due to thermal changes. Further, the temperature stabiliser can be adapted so that the “zero point” of the sensor signal input to the trigger circuit remains at or close to half the supply voltage. A temperature stabilised signal is output from the temperature stabiliser circuit 305 which is input to a trigger circuit 306 corresponding to the arrangement described with reference to Figure 1. The trigger circuit 306 has a first output 307 which goes high if the Hall Effect sensor detects a magnetic field with a south polarity and a second output 308 that goes high if the Hall Effect sensor detects a magnetic field with a north polarity.

The type of sensor system depicted in Figure 3 can be incorporated in the control system of an AGV arranged to follow a magnetised metallic guidance strip. Such an AGV includes a magnetic sensor including an array of Hall Effect sensors arranged to detect the metallic strip and from this generate movement (steering and speed) controls. The magnetic sensor may be further adapted to detect additional control sections of the metallic strip on which control information is encoded. Such control information might provide instructions for the AGV to perform certain actions such as a forklift pick up or forklift set down operation. The control information is encoded by differently magnetising (e.g. north polarity or south polarity) specific blocks of the control sections. The magnetic sensor of the AGV is arranged to read such control sections by the array of Hall Effect sensors detecting the polarity of the blocks as the magnetic sensor array moves over them.

The control system of an AGV might contain multiple sensor systems of the type shown in

Figure 3, for example, one for every Hall Effect sensor in the array of Hall Effect sensors. Each sensor system functions within this arrangement by outputting logical signals on the first and second outputs depending on the polarity of the detected magnetic field as discussed above. The logical signals output by the sensor system are received and processed by a processor unit.

Figure 4 shows a circuit arrangement 401 which corresponds to that shown in Figure 1 except that an adapted first buffer circuit and an adapted second buffer circuit are provided. The adapted first buffer circuit 402 includes a series arrangement of a first inverting buffer 403 and a second inverting buffer 404 rather than a single non-inverting buffer. The output 405 of the adapted first buffer circuit 402 is taken from the output of the first inverting buffer 403. The feedback resistor 406 of the first adapted buffer circuit is positioned across the output of the second inverting-buffer 404 and the input of the first inverting buffer 403.

Similarly, the adapted second buffer circuit 407 includes a series arrangement of a third inverting buffer 408 and a fourth inverting buffer 409 rather than a single non-inverting buffer. The output 510 of the adapted second buffer circuit 402 is taken from the output of the fourth inverting buffer 409. The feedback resistor 511 of the first adapted buffer circuit is positioned across the output of the fourth inverting-buffer 409 and the input of the third inverting buffer 408.

The embodiments of the circuit arrangement detailed above have been described in terms of receiving an input signal from a Hall Effect sensor and converting that input to a logical output which indicates if no magnetic field is detected, if a magnetic field with a south polarity is detected. However, it will be understood that circuit arrangements in accordance with certain embodiments of the invention are suitable for use with other sensors. In particular sensors which can be adapted to provide an output sensor signal with a “zero level” (i.e. no signal detected) which is half the supply voltage of the circuit arrangement. Accordingly, circuit arrangements in accordance with embodiments of the invention are suitable for use with many analogue sensors, for example noise sensors, ultrasonic sensors, infrasonic sensors, optical sensors, magnetic sensors, electromagnetic sensors, electrostatic sensors, static sensors, capacitance sensors, movement sensors, gyroscopic sensors, temperature sensors, shock wave sensors, x-ray sensors, Giger sensors, and moisture sensors and so on.

Features, integers, characteristics or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of the features and/or steps are mutually exclusive. The invention is not restricted to any details of any foregoing embodiments. The invention extends to any novel one, or novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

The reader’s attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims

1. A circuit arrangement for converting an input signal generated by a sensor to a logic output, said circuit arrangement comprising:

a voltage divider between a supply potential and a ground connection comprising first and second resistive load connected in series;

a sensor input line connected between the first and second resistive load, and first and second buffer circuits, an input of the first buffer circuit connected to the voltage divider between the sensor input line and the supply potential, and an input of the second buffer circuit connected to the voltage divider between the sensor input line and the ground connection, wherein each buffer circuit comprises a buffer and a feedback resistive load connecting an output of the buffer to the input of the buffer.

2. A circuit arrangement according to claim 1, wherein the buffer of each buffer circuit is provided by a non-inverting buffer.

3. A circuit arrangement according to claim 2, wherein the first buffer circuit further comprises an inverter connected to an output of the non-inverting buffer.

4. A circuit arrangement according to claim 1, wherein the buffer of each buffer circuit is provided by two inverting buffers in series.

5. A circuit arrangement according to any of claims 1 to 4, wherein an output of the first buffer circuit goes high if an input voltage on the sensor input line drops below a first voltage level and goes low if the input voltage on the sensor input line subsequently rises above a second voltage level, and an output of the second buffer circuit goes high if an input voltage on the sensor input line rises above a third voltage level, and goes low if the input voltage on the sensor input lines subsequently drops below a fourth voltage level.

6. A circuit arrangement according to claim 7, wherein the second voltage level is above the first voltage level, and the third voltage level is above the fourth voltage level.

7. A circuit arrangement according to claim 6, wherein the first voltage level is below the fourth voltage level and the third voltage level is above the second voltage level.

8. A circuit arrangement according to any of claims 5 to 7, wherein a value of the feedback resistive load of the first buffer circuit determines a voltage separation between the first voltage level and the second voltage level, and a value of the feedback resistive load of the first buffer circuit determines a voltage separation between the third voltage level and the fourth voltage level.

9. A circuit arrangement according to any previous claim, wherein the first resistive load comprises a first resistor and first potentiometer in series and the input of the first buffer circuit is connected to the voltage divider via the first potentiometer.

10. A circuit arrangement according to claim 9, wherein a value set on the first potentiometer determines a voltage level of the first voltage and the second voltage level.

11. A circuit arrangement according to claim any previous claim, wherein the second resistive load comprises a second resistor and second potentiometer in series and the input of the second buffer circuit is connected to the voltage divider via the second potentiometer.

12. A circuit arrangement according to claim 11, wherein a value set on the second potentiometer determines a voltage level of the third voltage and the fourth voltage level.

13. A circuit arrangement according to any previous claim, wherein the input of the first and second buffer circuits are capacitively coupled to ground by a capacitive coupling.

14. A circuit arrangement according to any previous claim, wherein a zero-point of the input signal generated by the sensor is substantially half the supply potential.

15. A sensor system comprising a sensor coupled to a circuit arrangement according to any of claims 1 to 14.

16. A sensor system according to claim 15, wherein the sensor is a Hall Effect sensor.

17. A circuit arrangement or sensor system, substantially as hereinbefore described with reference to the drawings.

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Application No: GB1621366.2