GB2553424B - Compilation for node device GPU-based parallel processing - Google Patents
Compilation for node device GPU-based parallel processingInfo
- Publication number
- GB2553424B GB2553424B GB1712171.6A GB201712171A GB2553424B GB 2553424 B GB2553424 B GB 2553424B GB 201712171 A GB201712171 A GB 201712171A GB 2553424 B GB2553424 B GB 2553424B
- Authority
- GB
- United Kingdom
- Prior art keywords
- compilation
- node device
- parallel processing
- based parallel
- device gpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
- G06F8/456—Parallelism detection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5055—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering software capabilities, i.e. software resources associated or available to the machine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5072—Grid computing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1001—Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers
- H04L67/1004—Server selection for load balancing
- H04L67/1008—Server selection for load balancing based on parameters of servers, e.g. available memory or workload
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/561—Adding application-functional data or data for application control, e.g. adding metadata
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/509—Offload
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Mathematical Physics (AREA)
- Library & Information Science (AREA)
- Debugging And Monitoring (AREA)
- Devices For Executing Special Programs (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Stored Programmes (AREA)
- Advance Control (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662379512P | 2016-08-25 | 2016-08-25 | |
US201662394411P | 2016-09-14 | 2016-09-14 | |
US15/422,285 US9760376B1 (en) | 2016-02-01 | 2017-02-01 | Compilation for node device GPU-based parallel processing |
Publications (3)
Publication Number | Publication Date |
---|---|
GB201712171D0 GB201712171D0 (en) | 2017-09-13 |
GB2553424A GB2553424A (en) | 2018-03-07 |
GB2553424B true GB2553424B (en) | 2018-11-21 |
Family
ID=59778869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1712171.6A Active GB2553424B (en) | 2016-08-25 | 2017-07-28 | Compilation for node device GPU-based parallel processing |
Country Status (9)
Country | Link |
---|---|
CN (1) | CN107783782B (en) |
BE (1) | BE1025002B1 (en) |
CA (1) | CA2974556C (en) |
DE (1) | DE102017213160B4 (en) |
DK (1) | DK179709B1 (en) |
FR (1) | FR3055438B1 (en) |
GB (1) | GB2553424B (en) |
HK (1) | HK1245439B (en) |
NO (1) | NO343250B1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111327921A (en) * | 2018-12-17 | 2020-06-23 | 深圳市炜博科技有限公司 | Video data processing method and device |
CN109743453B (en) * | 2018-12-29 | 2021-01-05 | 出门问问信息科技有限公司 | Split screen display method and device |
CN110163791B (en) * | 2019-05-21 | 2020-04-17 | 中科驭数(北京)科技有限公司 | GPU processing method and device of data computation flow graph |
CN111984322B (en) * | 2020-09-07 | 2023-03-24 | 北京航天数据股份有限公司 | Control instruction transmission method and device |
CN112783506B (en) * | 2021-01-29 | 2022-09-30 | 展讯通信(上海)有限公司 | Model operation method and related device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110252411A1 (en) * | 2010-04-08 | 2011-10-13 | The Mathworks, Inc. | Identification and translation of program code executable by a graphical processing unit (gpu) |
US20140333638A1 (en) * | 2013-05-09 | 2014-11-13 | Advanced Micro Devices, Inc. | Power-efficient nested map-reduce execution on a cloud of heterogeneous accelerated processing units |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8134561B2 (en) * | 2004-04-16 | 2012-03-13 | Apple Inc. | System for optimizing graphics operations |
US8549500B2 (en) * | 2007-02-14 | 2013-10-01 | The Mathworks, Inc. | Saving and loading graphical processing unit (GPU) arrays providing high computational capabilities in a computing environment |
US8938723B1 (en) * | 2009-08-03 | 2015-01-20 | Parallels IP Holdings GmbH | Use of GPU for support and acceleration of virtual machines and virtual environments |
US8310492B2 (en) * | 2009-09-03 | 2012-11-13 | Ati Technologies Ulc | Hardware-based scheduling of GPU work |
DE102013208418A1 (en) * | 2012-05-09 | 2013-11-14 | Nvidia Corp. | Method for producing executable data file in computer system, involves linking compiled device codes and host codes to generate linked device code and linked host code that are used for producing executable data file |
EP2887219A1 (en) * | 2013-12-23 | 2015-06-24 | Deutsche Telekom AG | System and method for mobile augmented reality task scheduling |
US9632761B2 (en) * | 2014-01-13 | 2017-04-25 | Red Hat, Inc. | Distribute workload of an application to a graphics processing unit |
US9235871B2 (en) * | 2014-02-06 | 2016-01-12 | Oxide Interactive, LLC | Method and system of a command buffer between a CPU and GPU |
-
2017
- 2017-07-26 CA CA2974556A patent/CA2974556C/en active Active
- 2017-07-27 BE BE2017/5528A patent/BE1025002B1/en active IP Right Grant
- 2017-07-28 FR FR1757193A patent/FR3055438B1/en active Active
- 2017-07-28 GB GB1712171.6A patent/GB2553424B/en active Active
- 2017-07-31 DE DE102017213160.8A patent/DE102017213160B4/en active Active
- 2017-08-01 NO NO20171277A patent/NO343250B1/en unknown
- 2017-08-01 CN CN201710647374.6A patent/CN107783782B/en active Active
- 2017-08-01 DK DKPA201770596A patent/DK179709B1/en active IP Right Grant
-
2018
- 2018-04-04 HK HK18104475.6A patent/HK1245439B/en unknown
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110252411A1 (en) * | 2010-04-08 | 2011-10-13 | The Mathworks, Inc. | Identification and translation of program code executable by a graphical processing unit (gpu) |
US20140333638A1 (en) * | 2013-05-09 | 2014-11-13 | Advanced Micro Devices, Inc. | Power-efficient nested map-reduce execution on a cloud of heterogeneous accelerated processing units |
Also Published As
Publication number | Publication date |
---|---|
GB201712171D0 (en) | 2017-09-13 |
HK1245439B (en) | 2019-12-06 |
BE1025002B1 (en) | 2018-09-17 |
NO343250B1 (en) | 2018-12-27 |
CA2974556A1 (en) | 2018-02-25 |
BE1025002A1 (en) | 2018-09-14 |
FR3055438B1 (en) | 2022-07-29 |
CA2974556C (en) | 2018-06-05 |
GB2553424A (en) | 2018-03-07 |
DE102017213160B4 (en) | 2023-05-25 |
CN107783782B (en) | 2019-03-15 |
NO20171277A1 (en) | 2018-02-26 |
DE102017213160A1 (en) | 2018-03-01 |
FR3055438A1 (en) | 2018-03-02 |
DK201770596A1 (en) | 2018-03-12 |
CN107783782A (en) | 2018-03-09 |
DK179709B1 (en) | 2019-04-09 |
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