GB2550019A - Prevention of switching discontinuity in a hybrid switched mode amplifier - Google Patents
Prevention of switching discontinuity in a hybrid switched mode amplifier Download PDFInfo
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- GB2550019A GB2550019A GB1703492.7A GB201703492A GB2550019A GB 2550019 A GB2550019 A GB 2550019A GB 201703492 A GB201703492 A GB 201703492A GB 2550019 A GB2550019 A GB 2550019A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2178—Class D power amplifiers; Switching amplifiers using more than one switch or switching amplifier in parallel or in series
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
- H03F1/0222—Continuous control by using a signal derived from the input signal
- H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
- H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/432—Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
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Abstract
A hybrid switched mode amplifier (20 fig 3) is described, capable of driving audio transducers, comprising a signal splitter (22), a first control loop (buck/boost converter 26 figure 4) acting on signal segment VIN_1 (figures 3,6) of input Vin and a second control loop 28 acting on signal segments VPRE, VIN_2 and Vin. The invention relates to the second control loop 28 which comprises first and second signal processing paths (VPC-to-Vout+, Vin-to-Vout-) providing a differential output load voltage Vout (Vout+/Vout-). The system further controls the switches 54,56,58,59/64,66,68,70 of a switching full-bridge to commutate polarity of a capacitor (52/62) with respect to first and second processing paths based on a commutation condition, e.g when Vout is non-zero. The second processing path loop compares Vout and Vin to provide Vout- via a linear amplifier 60. In addition a feedforward compensation VIN_2, VPRE is applied which bypasses second processing path loop filter 44 and prevents loop-filter compensating discontinuities caused by commutating capacitor (fig 7). The second processing path may further comprise a low pass filter comprising a capacitor 52 and resistor 48 coupled to the output of the loop filter, such that the feedforward compensation VIN_2, VPRE is inserted between the output of the loop filter 44 and the low-pass filter 48,52,54-58. The system enables integration of a consumer audio amplifier into mobile-devices, without incurring large filter components (capacitors). It utilises efficient switch-mode audio amplifiers in parallel with linear audio amplifiers. The low-pass-filter acts as a high-pass filter for the first processing path and passes high frequency converter ripple signals to both terminals of the differential output, eliminating costly filtering.
Description
PREVENTION OF SWITCHING DISCONTINUITY IN A HYBRID SWITCHED
MODE AMPLIFIER
FIELD OF DISCLOSURE
The present disclosure relates in general to circuits for audio devices, including without limitation personal audio devices such as wireless telephones and media players, and more specifically, to a switched mode amplifier including a switched mode converter for driving an audio transducer of an audio device.
BACKGROUND
Personal audio devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuitry often includes a speaker driver including a power amplifier for driving an audio output signal to headphones or speakers.
SUMMARY
In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with existing approaches to driving an audio output signal to an audio transducer may be reduced or eliminated.
In accordance with embodiments of the present disclosure, a signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, may be provided. The signal processing system may include a first processing path configured to process a first signal derived from an input signal to generate a first path voltage at a first processing path output, a second processing path configured to process a second signal derived from the input signal to generate a second path voltage at a second processing path output, wherein the second processing path comprises a feedback control loop having a loop filter, wherein the feedback control loop is configured to generate the second load voltage based on the input signal and the load voltage, a capacitor having a first capacitor terminal and a second capacitor terminal, a switching full-bridge, and a controller. The switching full-bridge may include a first plurality of switches, comprising at least a first switch coupled between the first processing path output and the first capacitor terminal and a second switch coupled between the first processing path output and the second capacitor terminal, and a second plurality of switches, comprising at least a third switch coupled between the second processing path output and the first capacitor terminal and a fourth switch coupled between the second processing path output and the second capacitor terminal. The controller may be configured to control switches of the switching full-bridge to commutate polarity of the capacitor with respect to the first processing path output and the second processing path output in response to a condition for commutating connectivity of the switching full-bridge and insert a feedforward compensation that bypasses the loop filter in order to prevent discontinuities caused by commutating polarity of the capacitor from being compensated by the loop filter.
In accordance with these and other embodiments of the present disclosure, a method for producing a load voltage at a load output of a signal processing system, wherein the load output comprising a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, may be provided. The signal processing system may include a first processing path configured to process a first signal derived from an input signal to generate a first path voltage at a first processing path output, a second processing path configured to process a second signal derived from the input signal to generate a second path voltage at a second processing path output, wherein the second processing path comprises a feedback control loop having a loop filter, wherein the feedback control loop is configured to generate the second load voltage based on the input signal and the load voltage, a capacitor having a first capacitor terminal and a second capacitor terminal, and a switching full-bridge. The switching full-bridge may include a first plurality of switches, comprising at least a first switch coupled between the first processing path output and the first capacitor terminal and a second switch coupled between the first processing path output and the second capacitor terminal, and a second plurality of switches, comprising at least a third switch coupled between the second processing path output and the first capacitor terminal and a fourth switch coupled between the second processing path output and the second capacitor terminal. The method may include controlling switches of the switching full-bridge to commutate polarity of the capacitor with respect to the first processing path output and the second processing path output in response to a condition for commutating connectivity of the switching full-bridge and inserting a feedforward compensation that bypasses the loop filter in order to prevent discontinuities caused by commutating polarity of the capacitor from being compensated by the loop filter.
Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein: FIGURE 1 illustrates an example personal audio device, in accordance with embodiments of the present disclosure; FIGURE 2 illustrates a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure; FIGURE 3 illustrates a block and circuit diagram of selected components of an example switched mode amplifier, in accordance with embodiments of the present disclosure; FIGURE 4 illustrates a circuit diagram of selected components of an example control loop that may be used to implement the first control loop depicted in FIGURE 3, in accordance with embodiments of the present disclosure; FIGURE 5 illustrates a circuit diagram of selected components of an example control loop that may be used to implement the second control loop depicted in FIGURE 3, in accordance with embodiments of the present disclosure; FIGURE 6 illustrates a graph depicting the relationship of a voltage driven by the first control loop depicted in FIGURE 3 and a voltage driven by a linear amplifier of the output stage depicted in FIGURE 3 as a function of a desired output voltage, in accordance with embodiments of the present disclosure; and FIGURE 7 illustrates a graph depicting the relationship of a voltage driven by the first control loop depicted in FIGURE 3 and a voltage driven by a linear amplifier of the output stage depicted in FIGURE 3 as a function of time, in accordance with embodiments of the present disclosure.
DETAILED DESCRIPTION FIGURE 1 illustrates an example personal audio device 1, in accordance with embodiments of the present disclosure. FIGURE 1 depicts personal audio device 1 coupled to a headset 3 in the form of a pair of earbud speakers 8A and 8B. Headset 3 depicted in FIGURE 1 is merely an example, and it is understood that personal audio device 1 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers. A plug 4 may provide for connection of headset 3 to an electrical terminal of personal audio device 1. Personal audio device 1 may provide a display to a user and receive user input using a touch screen 2, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device 1. As also shown in FIGURE 1, personal audio device 1 may include an audio integrated circuit (IC) 9 for generating an analog audio signal for transmission to headset 3 and/or another audio transducer. FIGURE 2 illustrates a block diagram of selected components of an example audio IC 9 of a personal audio device, in accordance with embodiments of the present disclosure. As shown in FIGURE 2, a microcontroller core 18 may supply a digital audio input signal DIG IN to a digital-to-analog converter (DAC) 14, which may convert the digital audio input signal to an analog signal Vin. DAC 14 may supply analog signal Vin to an amplifier 16 which may amplify or attenuate audio input signal Vin to provide a differential audio output signal Vout, which may operate a speaker, a headphone transducer, a line level signal output, and/or other suitable output. In some embodiments, DAC 14 may be an integral component of amplifier 16. A power supply 10 may provide the power supply rail inputs of amplifier 16. In some embodiments, power supply 10 may comprise a battery. Although FIGURES 1 and 2 contemplate that audio IC 9 resides in a personal audio device, systems and methods described herein may also be applied to electrical and electronic systems and devices other than a personal audio device, including audio systems for use in a computing device larger than a personal audio device, an automobile, a building, or other structure. FIGURE 3 illustrates a block and circuit diagram of selected components of an example switched mode amplifier 20, in accordance with embodiments of the present disclosure. In some embodiments, switched mode amplifier 20 may implement all or a portion of amplifier 16 described with respect to FIGURE 2. As shown in FIGURE 3, switched mode amplifier 20 may comprise a signal splitter 22, a first control loop 26, and a second control loop 28.
Signal splitter 22 may comprise any system, device, or apparatus configured to receive audio input signal Vin (or a derivative thereof) and generate a first signal Vin_i derived from audio input signal Vin and generate a second signal Vin_2 derived from audio input signal Vin, wherein second signal Vin 2 comprises information of the input signal absent from first signal Vin_i (e g., Vin 2 = Vin - Vin 1). For example, in some embodiments, first signal Vin 1 and second signal Vin 2 may be governed by the following set of equations:
where Vs at in represents a lower saturation voltage of audio input signal Vin which may be related to a lower saturation voltage of a power converter implemented by first control loop 26, as described in greater detail below.
In addition to the foregoing, signal splitter 22 may also generate a precompensation voltage signal Vpre, which may be communicated to control loop 28. The value of precompensation voltage signal Vpre is discussed in greater detail below with respect to FIGURE 5.
First control loop 26 may receive first signal Vin 1 at its input and may generate at its output a voltage Vpc as a function of first signal Vin 1. Turning briefly to FIGURE 4, FIGURE 4 illustrates a circuit diagram of selected components of an example control loop 26 that may be used to implement first control loop 26 depicted in FIGURE 3, in accordance with embodiments of the present disclosure. As shown in FIGURE 4, first control loop 26 may comprise a loop filter 32 and a power converter 40.
Loop filter 32 may comprise any system, device, or apparatus configured to receive an input signal (e.g., first signal Vin1 or a derivative thereof) and a feedback signal (e.g., voltage Vpc, a derivative thereof, or other signal indicative of signal Vpc) and based on such input signal and feedback signal, generate a controller input signal to be communicated to converter controller 34. In some embodiments, such controller input signal may comprise a signal indicative of an integrated error between the input signal and the feedback signal. In other embodiments, such controller input signal may comprise a signal indicative of a target voltage signal to be driven as voltage Vpc or a target current signal to be driven by power converter 40.
Converter controller 34 may comprise any system, device, or apparatus configured to, based on an input signal (e.g., output signal of loop filter 32), voltage Vpc, and/or other characteristics of first control loop 26, control switching of switches integral to power converter 40, in order to cause first control loop 26 to generate voltage Vpc as a function of first signal Vin_i.
As shown in FIGURE 4, power converter 40 may include a power inductor 42, and switches 44, 46, 47, and 49 arranged as shown. In some embodiments, a voltage Vsupply (e.g., provided by power supply 10 depicted in FIGURE 2) may be received via input terminals including a positive input terminal and a negative input terminal which may be coupled to a ground voltage. Accordingly, in operation, converter controller 34 may be configured to control switches 44, 46, 47, and 49 in order to convert voltage Vsupply to voltage Vpc, such that voltage Vpc is a function of first signal Vin_i to loop filter 32.
Turning again to FIGURE 3, second control loop 28 may receive at its inputs voltage Vpc generated by first control loop 26, second signal Vin 2, and audio input signal Vin, and based thereon may generate at its output audio output signal Vout. As described in greater detail in this disclosure (including, without limitation, in reference to FIGURE 5, below), second control loop 28 may comprise at least one linear amplifier and, in some embodiments, a plurality of switches, wherein the at least one linear amplifier and the plurality of switches, if present, are controlled by a loop filter in order generate audio output signal Vout based on voltage Vpc, second signal Vin_2, and audio input signal Vin, such that audio output signal Vout is a function of audio input signal Vin. FIGURE 5 illustrates a circuit diagram of selected components of an example control loop 28 that may be used to implement second control loop 28 depicted in FIGURE 3, in accordance with embodiments of the present disclosure. As shown in FIGURE 5, second control loop 28 may comprise a loop filter 44, a linear amplifier 60, an output capacitor 62, a first full-switching bridge comprising switches 64, 66, 68, and 70, a switched capacitor 52, and a second full-switching bridge comprising switches 54, 56, 58, and 59.
Loop filter 44 may comprise any system, device, or apparatus configured to receive an input signal (e.g., audio input signal Vin or a derivative thereof) and a feedback signal (e g., audio output signal Vout, a derivative thereof, or other signal indicative of audio output signal Vout) and based on such input signal and feedback signal, generate a filtered error signal Verr to be combined with second signal Vin_2 and communicated to linear amplifier 60. In some embodiments, such filtered error signal Verr may comprise a signal indicative of an integrated error between the input signal and the feedback signal. In other embodiments, such filtered error signal Verr may comprise a signal that when combined with second signal Vin_2 is indicative of a target voltage signal to be driven as linear output voltage Vamp. In these and other embodiments, loop filter 44 may include control circuitry and may drive control circuitry for controlling switches 54, 56, 58, 59, 64, 66, 68, and 70, in order to cause second control loop 28 to generate audio output signal Vout as a function of voltage Vpc and second signal Vin_2 (and thus a function of audio input signal Vin).
As shown in FIGURE 5, first control loop 26 may drive voltage Vpc which is received by second control loop 28. Accordingly, first control loop 26 may be considered a first processing path configured to process a first signal (e g., first signal Vin_i) derived from an input signal (e.g., audio input signal Vin) to generate a first path voltage (Vpc) at a first processing path output (e.g., output of first control loop 26).
Switch 64 may be coupled between the output of first control loop 26 and a first load terminal of second control loop 28, and switch 66 may be coupled between the output of first control loop 26 and a second load terminal of second control loop 28. Linear amplifier 60 may be configured to drive a linear amplifier output voltage Vamp which is a function of the filtered error signal Verr generated by loop filter 44. Switch 68 may be coupled between the output of linear amplifier 60 and the first load terminal of second control loop 28, and switch 70 may be coupled between the output of linear amplifier 60 and the second load terminal of second control loop 28. Output capacitor 62 may be coupled between a first load terminal (e.g., positive terminal of audio output signal Vout) and a second load terminal (e.g., negative terminal of audio output signal Vout). Accordingly, linear amplifier 60 may be considered a second processing path configured to process a second signal (e.g. second signal Vin 2) derived from an input signal (e.g., audio input signal Vin) to generate a second path voltage (Vamp) at a second processing path output (e.g., output of linear amplifier 60). In addition, the first fullswitching bridge may accordingly include a first plurality of switches (e.g., 64 and 66) comprising at least a first switch (e.g., 64) coupled between the first processing path output and a first load terminal, and a second switch (e.g., 66) coupled between the first processing path output and a second load terminal and a second plurality of switches (e.g., 68 and 70) comprising at least a third switch (e.g., 68) coupled between the second processing path output and the first load terminal and a fourth switch (e.g., 70) coupled between the second processing path output and the second load terminal.
In operation of second control loop 28, loop filter 44 or another controller may activate switches 64 and 70 and deactivate switches 66 and 68 for positive values of audio output signal Vout and activate switches 66 and 68 and deactivate switches 64 and 70 for negative values of audio output signal Vout. Loop filter 44 or such other controller may, as power converter output voltage Vpc approaches its lower saturation limit, cause linear amplifier 60 to drive a non-zero linear amplifier output voltage Vamp in order to increase a common mode voltage between the first output terminal and the second output terminal, allowing audio output signal Vout to approach and cross zero. Above the lower saturation limit of power converter output voltage Vpc, converter controller 34 may cause linear amplifier 60 to drive an approximately zero linear amplifier output voltage Vamp such that a magnitude of audio output signal Vout is equal to power converter output voltage Vpc.
In other words, first control loop 26 and linear amplifier 60 may be controlled to generate voltages in accordance with the following functions, which are graphically depicted in FIGURE 6, and wherein voltage Vtgt represents a target or desired voltage to be output as audio output signal Vout:
In some embodiments, an offset voltage may be added to each of the output of first control loop 26 and the output of linear amplifier 60, to ensure that the voltage Vamp > 0 at all times.
Accordingly, presence of linear amplifier 60 and its ability to increase the common mode voltage of the output terminals in response to low magnitudes of the output signal Vout may minimize non-linearities of audio output signal Vout as a function of audio input signal Vin, and permit crossing a magnitude of zero by audio output signal Vout.
With respect to the second full-switching bridge, switch 54 may be coupled between the output of first control loop 26 and a first terminal of switching capacitor 52, and switch 56 may be coupled between the output of first control loop 26 and a second load of switching capacitor 52. Switch 58 may be coupled between the input of linear amplifier 60 and the first terminal of switching capacitor 52, and switch 59 may be coupled between the input of linear amplifier 60 and the second terminal of switching capacitor 52. Accordingly, the second full-switching bridge may include a third plurality of switches (e.g., 54 and 56) comprising at least a fifth switch (e.g., 54) coupled between the first processing path output (e.g., output of first control loop 26) and a first capacitor terminal and a sixth switch (e.g., 56) coupled between the first processing path output and the second capacitor terminal and a fourth plurality of switches (e.g., 58 and 59) comprising at least a seventh switch (e.g., 58) coupled between a second processing path input (e.g., input of linear amplifier 60) and the first capacitor terminal and an eighth switch (e.g., 59) coupled between the second processing path input and the second capacitor terminal.
In operation of second control loop 28, loop filter 44 or another controller may control switches 54, 56, 58, and 59 of the second switching full-bridge such that when switches 64, 66, 68, and 70 of the first switching full-bridge are switched to reverse connectivity of the output of first control loop 26 and the output of linear amplifier 60 to the first load terminal and the second load terminal as described above, switches 54, 56, 58, and 59 of the second switching full-bridge may be switched substantially contemporaneously with switching of switches 64, 66, 68, and 70 of the first switching full-bridge to reverse connectivity of the output of first control loop 26 and the input of linear amplifier 60 to the terminals of switching capacitor 52 in order to minimize voltage discontinuities caused by the switching of switches 64, 66, 68, and 70 of the first switching full-bridge.
To further illustrate the effect of such switching, FIGURE 7 illustrates a graph depicting the relationship of voltage Vpc driven by first control loop 26 and voltage driven by a linear amplifier 60 as a function of time, in accordance with embodiments of the present disclosure. FIGURE 7 depicts such signal voltages during a time when a magnitude of audio output signal Vout is less than the lower saturation value of voltage Vpc. Accordingly, during such time, first control loop 26 may output voltage Vpc having a direct-current value of lower saturation voltage Vsat with a high-frequency ripple component superimposed as shown in FIGURE 7. As audio output signal Vout increases from a negative polarity to cross zero and increase to positive values, the voltage Vout" at the negative terminal of the output of second control loop 28 generated by linear amplifier 60 (e.g., voltage Vamp which is passed through switches 68 and 70 depending on states of such switches) may have a waveform as depicted in FIGURE 7. As seen in FIGURE 7, so that voltage Vamp may maintain a positive value above zero, commutation of the first full-switching bridge of switches 64, 66, 68, and 70 may occur when audio output signal Vout is non-zero, as shown at time to in FIGURE 7. When such output polarity transition occurs at non-zero audio output signal Vout, linear amplifier 60 must immediately transition from supplying a voltage that is AVi greater than output voltage Vpc to a voltage that is AV2 lesser than output voltage Vpc. In order to minimize discontinuity in audio output signal Vout, AVi must be maintained approximately equal to AV2.
Referring again to FIGURE 5, a low-pass filter comprising resistance 48 and capacitor 52 may create a significant delay path in second control loop 28, such that if the transition of the first full-switching bridge of switches 64, 66, 68, and 70 is driven solely by second control loop 28, the delays imposed by the low-pass filter may now allow for fast resolution of the discontinuity. However, by commutating the second full-switching bridge of switches 54, 56, 58, and 59 substantially contemporaneously with the first fullswitching bridge of switches 64, 66, 68, and 70, such delay may be alleviated.
In addition, while switching capacitor 52 and resistance 48 may effectively form a low-pass filter as seen from the output of loop filter 44, switching capacitor 52 and resistance 48 may effectively form a high-pass filter as seen from the output of control loop 26. Accordingly, high-frequency components of voltage Vpc, such as the high-frequency ripple depicted in FIGURE 7, may be capacitively coupled into the input of linear amplifier 60, such that the high-frequency components are coupled (e.g., in a feedforward manner) into the input of linear amplifier 60 and passed to linear amplifier output voltage Vamp, such that the high-frequency components of voltage Vpc are effectively cancelled out by voltage Vamp, and such that the high-frequency components of voltage Vpc are substantially absent from the load voltage. Accordingly, the feedback control loop of second control loop 28 may operate predominantly on low-frequency components of voltage Vpc and voltage Vamp below a corner frequency of the high-pass filter.
In an ideal case, the polarity of audio output signal Vout could be flipped at an exact zero-crossing point. However, monitoring and determining an exact zero-crossing is difficult, and to avoid oscillation, delay and hysteresis may need to be inserted, making monitoring and determining an exact zero-crossing even more difficult. In order to cause no effect on an output load coupled to the output of second control loop 28, at least one of voltage Vpc and voltage Vamp must have a sudden voltage step in order to maintain a proper voltage balance for audio output signal Vout. Without accounting for such sudden step, discontinuities caused by commutating polarity of capacitor 52 near a zero-crossing of audio output signal Vout may be undesirably compensated by loop filter 44, which may lead to decreased total harmonic distortion. Accordingly, when a condition for commutating connectivity of the switching full-bridge comprising switches 54, 56, 58, and 59 occurs (e g., a zero-crossing of audio output signal Vout), switches of the switching full-bridge comprising switches 54, 56, 58, and 59 may be controlled to commutate polarity of capacitor 52 with respect to voltage Vpc and the input to linear amplifier 60. However, in addition, further in response to such condition for commutating connectivity of the switching full-bridge comprising switches 54, 56, 58, and 59, precompensation voltage signal Vpre may be added between the output of loop filter 44 and the low-pass filter created by resistance 48 and capacitor 52. Insertion of precompensation voltage signal Vpre is thus insertion of a feedforward compensation that bypasses loop filter 44 in order to prevent discontinuities caused by commutation of the polarity of capacitor 52 from being compensated by loop filter 44. Thus, in response to a condition for commutating connectivity of the switching full-bridge comprising switches 54, 56, 58, and 59, signal splitter 22 may set precompensation voltage signal Vpre for a period of time (e.g., such period of time related to the bandwidth of loop filter 44) such that the equation VampO) = (Verr(0 + Vpre_Bw(t))A(t)B(t), where Vpre bw is precompensation voltage signal Vpre at a bandwidth of interest (e g., audio band of 20 kilohertz), A(t) is a transfer function of the low-pass filter created by resistance 48 and capacitor 52, and B(t) is a transfer function of linear amplifier 60. In the absence of the condition for commutating connectivity of the switching full-bridge, or after a period of time after the occurrence of condition for commutating connectivity of the switching full-bridge, signal splitter 22 may set the value of voltage signal Vpre to zero, as such compensation may not be needed during such periods.
As used herein, a “switch” may comprise any suitable device, system, or apparatus for making a connection in an electric circuit when the switch is enabled (e.g., activated, closed, or on) and breaking the connection when the switch is disabled (e.g., deactivated, open, or off) in response to a control signal received by the switch. For purposes of clarity and exposition, control signals for switches described herein are not depicted although such control signals would be present to selectively enable and disable such switches. In some embodiments, a switch may comprise a metal-oxide-semiconductor field-effect transistor (e.g., an n-type metal-oxide-semiconductor field-effect transistor).
As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.
This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.
All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.
Claims (10)
1. A signal processing system for producing a load voltage at a load output of the signal processing system, the load output comprising a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, the signal processing system comprising: a first processing path configured to process a first signal derived from an input signal to generate a first path voltage at a first processing path output; a second processing path configured to process a second signal derived from the input signal to generate a second path voltage at a second processing path output, wherein the second processing path comprises a feedback control loop having a loop filter, wherein the feedback control loop is configured to generate the second load voltage based on the input signal and the load voltage; a capacitor having a first capacitor terminal and a second capacitor terminal; a switching full-bridge comprising: a first plurality of switches, comprising at least a first switch coupled between the first processing path output and the first capacitor terminal and a second switch coupled between the first processing path output and the second capacitor terminal; and a second plurality of switches, comprising at least a third switch coupled between the second processing path output and the first capacitor terminal and a fourth switch coupled between the second processing path output and the second capacitor terminal; and a controller configured to: control switches of the switching full-bridge to commutate polarity of the capacitor with respect to the first processing path output and the second processing path output in response to a condition for commutating connectivity of the switching full-bridge; and insert a feedforward compensation that bypasses the loop filter in order to prevent discontinuities caused by commutating polarity of the capacitor from being compensated by the loop filter.
2. The signal processing system of Claim 1, wherein the second processing path comprises a low-pass filter coupled to the output of the loop filter, and wherein the feedforward compensation is inserted between the output of the loop filter and the low-pass filter.
3. The signal processing system of Claim 2, wherein the low-pass filter comprises the capacitor.
4. The signal processing system of Claim 1, wherein the condition for commutating connectivity of the switching full-bridge is when the load voltage is a substantially non-zero voltage.
5. The signal processing system of Claim 1, wherein the second processing path comprises a feedback control loop configured to generate the second load voltage based on the input signal and the load voltage.
6. A method for producing a load voltage at a load output of a signal processing system, the load output comprising a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, the signal processing system comprising: a first processing path configured to process a first signal derived from an input signal to generate a first path voltage at a first processing path output; a second processing path configured to process a second signal derived from the input signal to generate a second path voltage at a second processing path output, wherein the second processing path comprises a feedback control loop having a loop filter, wherein the feedback control loop is configured to generate the second load voltage based on the input signal and the load voltage; a capacitor having a first capacitor terminal and a second capacitor terminal; and a switching full-bridge comprising: a first plurality of switches, comprising at least a first switch coupled between the first processing path output and the first capacitor terminal and a second switch coupled between the first processing path output and the second capacitor terminal; and a second plurality of switches, comprising at least a third switch coupled between the second processing path output and the first capacitor terminal and a fourth switch coupled between the second processing path output and the second capacitor terminal; wherein the method comprises: controlling switches of the switching full-bridge to commutate polarity of the capacitor with respect to the first processing path output and the second processing path output in response to a condition for commutating connectivity of the switching full-bridge; and inserting a feedforward compensation that bypasses the loop filter in order to prevent discontinuities caused by commutating polarity of the capacitor from being compensated by the loop filter.
7. The method of Claim 6, wherein the second processing path comprises a low-pass filter coupled to the output of the loop filter, and wherein inserting the feedforward compensation comprises inserting the feedforward compensation between the output of the loop filter and the low-pass filter.
8. The method of Claim 7, wherein the low-pass filter comprises the capacitor.
9. The method of Claim 6, wherein the condition for commutating connectivity of the switching full-bridge is when the load voltage is a substantially nonzero voltage.
10. The method of Claim 6, wherein the second processing path comprises a feedback control loop configured to generate the second load voltage based on the input signal and the load voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662309068P | 2016-03-16 | 2016-03-16 | |
| US15/282,790 US9929664B2 (en) | 2016-03-16 | 2016-09-30 | Prevention of switching discontinuity in a hybrid switched mode amplifier |
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| Publication Number | Publication Date |
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| GB201703492D0 GB201703492D0 (en) | 2017-04-19 |
| GB2550019A true GB2550019A (en) | 2017-11-08 |
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| GB1703492.7A Withdrawn GB2550019A (en) | 2016-03-16 | 2017-03-03 | Prevention of switching discontinuity in a hybrid switched mode amplifier |
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| WO1998057422A1 (en) * | 1997-06-10 | 1998-12-17 | Cirrus Logic, Inc. | High-order multipath operational amplifier with dynamic offset reduction, controlled saturation current limiting, and current feedback for enhanced conditional stability |
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| US20160056707A1 (en) * | 2014-08-25 | 2016-02-25 | Linear Technology Corporation | Notch filter for ripple reduction |
| GB2546576A (en) * | 2016-01-18 | 2017-07-26 | Cirrus Logic Int Semiconductor Ltd | Hybrid switched mode amplifier |
| WO2017127132A1 (en) * | 2016-01-18 | 2017-07-27 | Cirrus Logic International Semiconductor, Ltd. | Switched mode converter with variable common mode voltage buffer |
| WO2017127353A1 (en) * | 2016-01-18 | 2017-07-27 | Cirrus Logic International Semiconductor, Ltd. | Hybrid switched mode amplifier |
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| WO1998057422A1 (en) * | 1997-06-10 | 1998-12-17 | Cirrus Logic, Inc. | High-order multipath operational amplifier with dynamic offset reduction, controlled saturation current limiting, and current feedback for enhanced conditional stability |
| US6617908B1 (en) * | 2002-03-22 | 2003-09-09 | Cirrus Logic, Inc. | Switched-capacitor circuits with reduced distortion |
| US20090212859A1 (en) * | 2006-06-30 | 2009-08-27 | Lesso John P | Amplifier circuit and methods of operation thereof |
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| GB201703492D0 (en) | 2017-04-19 |
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