GB2548052A

GB2548052A - Analogue to digital converter

Info

Publication number: GB2548052A
Application number: GB1709574.6A
Authority: GB
Inventors: Raymond Davies Jevon
Original assignee: Individual
Current assignee: Individual
Priority date: 2010-01-15
Filing date: 2010-01-15
Publication date: 2017-09-06
Anticipated expiration: 2030-01-15
Also published as: GB2548053A; GB201709574D0; GB2548053B; GB201709575D0; WO2011086378A1; GB2548054B; GB2478272A; GB201709576D0; GB2548054A; GB2548052B; GB201000690D0

Abstract

An analogue to digital converter 1 comprises a plurality of parallel-connected circuits 8a-n, each converting an analogue signal into a series of digital pulses. The number of pulses produced by each circuit in a time period is related to the integral of the analogue signals amplitude over that time period. Each circuit comprises an integrator (30, Figure 3) which integrates an analogue signal and has an output coupled to a first input of a comparator (40, Figure 2), wherein each integrator comprises a capacitor (32, Figure 2) of differing capacitance and/or the second input of each comparator is provided with a different reference voltage. The pulses generated by each circuit may be desynchronised with the pulses generated by other circuits. Each circuit may generate a respective analogue signal by adding a different bias signal or noise signal to an analogue input signal 2 so as to reduce the likelihood of pulses from two or more circuits from occurring at the same time. Each circuit may generate a pulse asynchronously when the integral of the integral of the input signal is equal to a predetermined reference voltage.

Description

ANALOGUE TO DIGITAL CONVERTER FIELD OF THE INVENTION The invention relates to an analogue to digital converter.

BACKGROUND OF THE INVENTION

Analogue to digital converters (ADCs) are essential elerrsersts of many electronic systems. Their purpose is to convert a signal in the analogue domain, i.e. a signal that is continuous in time and/or amplitude, into a digital expression, i.e. a number or sequence of numbers that are discrete in time and/or amplitude. Once the digital form of the signal is a vailable it is possible to apply a range of useful operations to the signal, which is commonly known as digital signal processing. The act of converting from the analogue domain to the digital dorr\ain is commonly referred to as sampling.

Several types of ADC are known, each having their own advantages and disadvantages. One type of ADC is the Flash ADC, in which a number of comparators simultaneously compare an analogue input signal to a number of different reference voltages. The Flash ADCi! is capable of fast analogue to digital conversion, but its resolution is limited by the number of comparators used, and increasing the number of comparators increases the size and cost of the ADC.

Another type of y\DC is the dual-slope ADC, in which an analogue input signal is applied to the input of an operational amplifier integrator for a fixed period of time so as to allow the integrator's output voltage to increase, and then a reference voltage is applied to the integrator's input until the output voltage returns to zero. The amplitude of the analogue input signal can then be calculated as a function of the period of time during which the analogue input signal was applied to the integrator, the reference voltage and the time taken for the output of the integrator to return to zero. Dual-slope ADCs require few electronic components, making them compact and cheap, and can have high resolutions. How'Cver, dual-slope ADCs require a relatively long time to perform analogue to digital conversion, which places an upper limit on the frequency of the input signal that can be sampled. A further type of ADC is the sigma-delta ADC. .A sigma-delta ADC comprises a differential amplifier, an integrator, a comparator, a 1-bit digital to analogue converter (DAC) and a counter. An analogue input signal is applied to the non-inverting input of the differential amplifier, the output of w^ich is integrated by the integrator. The output of the integrator is compared with a threshold voltage by the comparator, and the result is fed back to the inverting input of the differerhial amplifier via the DAC. This causes the comparator to generate a series of pulses, which are counted by the counter to derive a digital representation of the analogue input signal. Sigma-delta converters are susceptible to electrical noise in the sense that the presence of noise in the sigma-delta converter circuit can severely limit the accuracy of the digital representation that is produced. Funhermore, sigma-delta converters also need to oversample the analogue input signal to achieve good results (i.e. the sigma-delta converter must sample the analogue input signal at a frequency that is several times greater than the highest frequency component in the analogue input signal), which limits the ability of sigma-delta converters to sample ver\' high frequency input signals and requires sigma-delta converters to use components that are capable of operating at very' high frequencies.

All known ADCs are electronic devices which operate as deterministically as possible. That is, they operate according to a method that, in the absence of noise, would follow an exactly predictable path and would have an exactly predictable outcome. Given that all real electronic systems inherently have a finite level of electrical raoise, the extent to which kr\own ,'\DCs are successful depends on the level of noise relative to the other signals in the converter system. The presence of electrical noise can cause significant problems wher\ it is necessary to sample an analogue input signal at a high resolution in order to generate an accurate digital representation of the signal. For example, most industrial processes require signals to be sampled to 12 to 16 bit accuracy, audio signals for compact discs are sampled to 18 bit accuracy and geophysical (seismology) data often needs to be sampled to 24 to 26 bit accuracy. However, in most electrical circuits the noise level is at the tenth to twelfth bit; that is, most circuits inherently contain in excess of 5 millivolts of noise and, for an ADC having a 5 volt input range, the twelfth bit of the .AD(''s output represents Ή.2 millivolts. Hence, the presence of noise that is inherent in the analogue to digital converter itself causes problems whenever it is necessary to sample an input signal to greater than 10 bit accuracy.

There is a general progression to build electronic systems that work faster and/or consume less power. Being able to do this makes new technical and commercial opportunities feasible to exploit. However, given that the levels of noise in electronic systems are not reducible without limit, and given that lower power and higher speed circuits are more susceptible to noise, the electronics industry is approaching operating regimes in which the levels of noise are a significant barrier to the successful operation of conventional electronic systems.

SUMMARY OF THE INVENTION A preferred aim of the present invention is to provide an .ADC that is less susceptible to noise than known ADCs. Another preferred aim of the inverhion is to provide an ADC with a high sampling frequency, so as to allow' high frequency analogue signals to be converted to a digital form.

The invention provides an analogue to digital converter comprising a plurality of circuits eadi operable to convert an analogue signal into a series of digital pulses, wherein the number of pulses produced by each of the circuits in a particular time period is related to the integral of the amplitude of the analogue signal over that time period, w'herein the plurality of circuits are connected in parallel with each other and each comprises an integrator and a comparator, the integrator being arranged to integrate an aiialogue signal, the integrator having an output coupled to a first input of the comparator, and wherein: each integrator comprises a capacitor, wherein the capacitor of each circuit has a different capacitance value; and/or a different reference voltage is provided to a second input of each comparator.

The circuits are referred to in the following description as integrate-and-fire (I&F) units, The time period is referred to in the following description as the sampling inter\'al. Connecting a plurality of such circuits in parallel with each other filters noise in the analogue input signal, since the circuits will collectively average the noise towards zero. Furthermore, connecting a plurality of such circuits in parallel allows the analogue input signal to be sampled at a higher frequency than would be possible with a single circuit.

In the claims and description, there is a distinction between the term "analogue input signal" and the term "analogue signal". The term "analogue input signal" refers to the atialogue signal of interest, i.e, the signal that is to be converted to the digital domain. The term "analogue signal" refers to the signal that is converted into a series of pulses. The analogue signal is the sum of the analogue input signal, noise that is inherent in the analogue to digital converter itself, a bias input and, optionally, a noise signal that is deliberately added to the analogue input signal.

Each of the circuits is arranged to receive the same analogue input signal. Noise that is inherent in the analogue to digital converter itself w'ill mean that, whilst each circuit receives substantially the same "analogue input signal", each circuit will convert a different "analogue signal" into a series of digital pulses. Preferably the analogue to digital converter comprises means (such as appropriate interconnections) for receiving an analogue input signal and distributing the analogue input signal to each of the plurality of circuits. Preferably the analogue to digital converter comprises means (such as an OR gate or a circuit having equivalent functionality ) for collecting the digital pulses produced by all of the circuits, so as to provide a single output comprising all of the pulses.

The use of different capacitance values prevents synchronisation of the circuits yet does not require additional circuitry, thereby reducing the cost and complexity of the analogue to digital converter.

The provision of different reference voltages prevents synclironisation of the circuits yet does not require much additional circuitry, thereby reducing the cost and complexity of the analogue to digital converter. For example, different reference voltages can be generated with a simple resistive potential divider network.

Preferably the plurality of circuits are configured such that the pulses generated by each circuit are desynchronised with the pulses generated by other circuits. Preventing synchroni sation of the circuits ensures that the circuits collectively sample the analogue input signal throughout the sampling interv al. Preferably desynchronisation of the pulses generated by each circuit is achieved, at least in part, by the presence of noise that is inherent in analogue to digital converter itself. Preferably each of the circuits is configured to generate a respective analogue signal by adding a different bias signal to an analogue input signal. Preferably each of the circuits is configured to generate a respective analogue signal by adding a different noise signal to an analogue input signal. The addition of different bias signals and,/or different noise signals prevents synchronisation of the circuits yet does not require much additional circuitry, thereby reducing the cost and complexity of the analogue to digital converter. For example, different bias signals can be generated with a simple resistive potential divider network.

Preferably each of the circuits is operable to generate a pulse asynchronously when the integral of the integral of the input signal is equal to a predetermined reference voltage, it is advantageous for the ADC to operate asynchronously because asynchronous circuits are less complicated and consume less powder than synchroi\ous circuits.

The analogue to digital converter may comprise a counter for counting the total number of pulses produced by each of the plurality of circuits, 'fhe total number of pulses counted by the counter during the sampling interval is the result of the analogue to digital conversion, i.e. a digital representation of the analogue input signal.

The analogue to digital converter may comprise a reset input that, when activated, causes the counter to be reset. The provision of a reset input allows several important parameters of the analogue to digital converter to be controlled simply by resetting the counter at appropriate intervals, and without requiring any hardware modifications. The sampling rate of the analogue to digital converter may be determined by the frequency at w^ich the reset input is activated. The resolution of the analogue to digital converter may be determined by the frequency at which the reset input is activated. The analogue to digital converter may be operable to low'-pass filter the analogue input signal with a filter cut-off frequency determined by the frequency at which the reset input is activated.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred features of the invention will now be described, purely by way of example, with reference to the accompanying drawings, w'herein like elements will be indicated using like reference signs, and in which:

Fig. 1 is a schematic diagram of an example of an ADC in accordance with the present invention;

Fig, 2 is a circuit diagram of an example of an integrate-and-fire unit of the ADC shown in Fig. 1; and

Fig. 3 is a graph of voltage against time to illustrate the generation of pulses by two integrate-and-fire units in response to an analogue input signal.

DETAILED DESCRIPTION

The present application discloses a new' type of analogue to digital converter ( ADC) that is inherently stochastic in nature. This implies that its operation is not predictable in all respects, but that its output is a statistical function of its internal operations. Some of its internal operations may be deterministic, but some are not so, and therefore can only be predicted in a statistical fashion. Nonetheless, in the same way that the outcome of a random event such as the flipping of a coin can be predicted statistically with high accuracy for a large sample size, the output of the new ADC disclosed herein is statistically predictable in a usefoi range of operation.

Figure 1 is a schematic diagram of an .ADC 1 in accordance with the present invention. The ADC 1 comprises a buffer 4, a plurality of integrate-and-fire (I&F) units 8, an OR gate 12, a counter 16. An analogue input signal 2 is applied to the input of the buffer 4.

The buffer 4 is a circuit having a high input impedance, and is provided to avoid the ADC 1 loading the analogue input signal 2. 4 he buffer 4 may be implemented using an operational amplifier in a 'voltage follower' configuration, as is known in the art. The output 6 of the buffer 4 is connected to each of the plurality of I&F units 8a to 8n.

An I&F unit 8 is a circuit that converts an analogue signal into a series of digital pulses, wherein the number of digital pulses produced by the I&F unit in a given time period is related to (and, preferably, proportional to) the integral of the amplitude of the analogue signal over that time period. The I&F units 8 are connected in parallel with each other. The ADC 1 can comprise any number of I&F units 8, although better results are achieved by using a larger number of I&F units, at the expense of an increase in the size, cost and complexity of the ADC 1, A typical embodiment of the .ADC I comprises eight I&F units 8, The I&F units 8 are described in detail belowr The digital outputs 10a to lOn of each of the I&F units 8a to 8n are connected to the input of an OR gate 12.

The OR gate 12 is a circuit component that produces a logic T at its output w'hen one or more of its inputs is at logic T. The OR gate 12 can be implemented in any suitable manner known to those skilled in the art, and need r\ot corr\prise a logic gate in the traditional sense. For example, a simple network of transistors may instead be used to implement a logical OR function. The output 14 of the OR gate 12 is connected to a counter 16.

The counter 16 is a digital circuit component that converts a serial sequence of bits (i.e. logic O's and logic Ts) presented at its input 14 into a parallel digital word at its output 18, wherein the digital word corresponds to the number of logic Ts in the serial sequence of bits. The counter 16 is asynchronous, i.e. it does not require a clock signal in order to count the number of logic Ts in the serial sequence of bits. This can be achieved, for example, by implementing the counter such that it increments its count wher\ it detects the rising (or falling) edge of a logic T pulse at its input. The counter can be implemented in any suitable manner known in the art. The digital word generated at the output 18 of the counter 16 can comprise any number of bits. The output 18 of the counter 16 is connected to a digital system 20.

The digital system 20 is the circuit that ultimately uses the digital representation of the analogue input signal 2 and may include, for example, a memory, a microprocessor and,/or a digital signal processing chip. The digital system 20 has an output 22 connected to a reset input 21 of the counter 16 such that, when the digital system 20 presents an appropriate digital value on its output 22, the output 18 of the couiher 16 is reset to zero. The digital system 20 is preferably not a part of the ADC 1 itself, but is instead an external circuit that is connected to the ADC ]. However, the functionality of the digital system 20 that causes the counter 16 to be reset could be implemented in the ADC 1 itself, which would advantageously simplify the task of designing a circuit to control the ADC 1.

Whilst the counter 16 is illustrated as being part of the A.DC 1 in this example, it will be appreciated that an integrated circuit (1C) that implements the .ADC 1 described herein need not necessarily comprise a counter. Such an iC may have an output pin connected to the output 14 of the OR gate 12, so as to allow a circuit designer the fieedom to design an appropriate counter and control logic therefor.

The I&F units 8 will now be described with reference to Fig. 2, which is a circuit diagram of an example of a single I&F unit 8. The I&F unit 8 comprises an integrator 30 and a comparator 40.

The integrator 30 can be any electronic circuit capable of integrating an input signal i.e. producing an output signal whose amplitude is related to the integral of the input signal with respect to time. In the example showm in Fig, 2, the integrator 30 is implemented using an operational amplifier 31 having its non-inverting input connected to ground, its inverting input connected to an analogue signal 33 (i.e. the signal to be integrated), and having a capacitor 32 connected betw^een its output and inverting input. Additionally, an electronicaliy-activated switch 34 is connected between the output and inverting input of the operational amplifier 31. The switch 34 is normally in the open state but, when a control signal is applied to it (and, more particularly, wdien the switch 34 receives a logic T from the output 10 of the comparator 40, as will be described below), the switch 34 closes and short circuits the output and inverting input of the operational amplifier 31. An integrator configured in this manner is sometimes known as an "integrate and dump" circuit. The switch 34 can be implemented in any suitable manner known to those in the art, and may simply comprise a transistor such as a field effect transistor.

The analogue signal 33 that is input to the integrator 31 consists of three components; an analogue input signal, imput, a bias input, kias, and noise, inoisa· The analogue input signal, imp,a, is the signal of interest (i.e. the analogue signal that is to be converted to the digital domain) and is taken from the output 6 of the buffer 4 shown in Fig, 1.

The bias input, iipas, is a signal having a constant amplitude. The bias input, ih-as, enforces a drift direction and rate on the output 36 of the integrator 30, so that even in the absence of an analogue input signal, imput, the output 36 of the integrator 30 will tend in a specified direction. The purpose of the bias input, ib,as, is to avoid synchronisation of the I&F units 8, as will be discussed in more detail below.

The noise, inetse, is a signal whose amplitude varies randomly over time, inotte represents the electrical noise that is inherent in the ADC itself, which is added to the analogue input signal, imput, and/or bias input, ibtas, by circuit components and interconnections that are upstream of the integrator 31. Noise is detrimental to the performance of most electrical circuits, but the noise, inotae, is actually advantageous to the performance of the ADC disclosed herein, since it can help to avoid synchronisation of the i&F units 8, as will be discussed in more detail below. The noise that is inherent in the ADC itself can optionally be supplemented by the deliberate addition of a noise signal to the input of the integrator 31 using a noise-generating circuit. In this case, inoitte represents the sum of the electrical noise that is inherent in the .ADC itself and the noise signal that is deliberately added by the noise-generating circuit. For example, a suitable noise-generating circuit is an amplifier with a i1oatii\g input (i.e. an input that is not connected to a voltage or to ground), such that the amplifier will amplify and output the thermal i\oise that is inherently present at its floating input. The deliberate addition of a noise signal further helps to avoid synchronisation of the I&F units 8. It is not essential to add noise deliberately, since correct operation of the ADC can still be achieved by the noise that is inherent in the ADC itself However, it is sometimes desirable to provide a noisegenerating circuit in order to allow the amplitude of the noise to be controlled relative to the amplitude of the analogue input signal, imput- The noise, inoise, does not adversely affect the accuracy of the analogue to digital conversion because it has zero average amplitude over a given time period, and so the noise will be averaged towards zero when the i&F units 8 take multiple samples of the analogue input signal, U„put, during each sampling period in the manner described below.

The comparator 40 can be any electronic circuit capable of generating a digital output that depends upon the amplitude of the output 36 of the integrator 30 relative to the amplitude of a reference signal 38. For example, the comparator 40 can be implemented using an operational amplifier. The non-inverting input of the comparator 40 is connected to the output 36 of the integrator 30, and the inverting input of the comparator 40 is connected to a predetermined DC reference voltage 38. in this example, the output 10 of the comparator will be logic ’Γ when the output 36 of the integrator 30 is greater than the reference voltage 38, and will be logic '0' otherwdse. The output 10 of the comparator is connected to the switch 34 and to the OR gate 12 showm in Fig. 1.

The operation of an I&F unit 8 will now be described. The output 36 of the integrator 30 will reflect the analogue input 33, typically such that:

(1) wdiere v(t) is the voltage of the output 36 of the comparator 30 at time t, C is the capacitance of the integrating capacitor 32, and to is the time at wdiich the integrator 30 was last reset by means of the switch 34. For the purposes of this explanation, it can be assumed that the input current polarities (i.e, iinput, ihias and inotse) are chosen to produce a positive integrator output voltage. Thus, the output 36 of the comparator 30 will tend to increase over time.

When the output 36 of the integrator 30 reaches the reference voltage 38, the logic state of the output 10 of the comparator 40 changes (from logic '0' to logic T in the example shown in Fig. 2). As noted previously, the output 10 of the comparator 40 is fed back to the switch 34, wdiich resets the output 36 of the integrator 30 to zero, which in turn causes the output 10 of the comparator 40 to return to its original logic state (i.e. logic '0' in the example shown in Fig. 2). The overall effect is to produce a momentary pulsed output from the comparator 40 at the moment that the output 36 of the integrator 30 becomes equal to the reference voltage 38. The output 36 of the integrator 30 will have an approximately sawhooth waveform.

The rate at w'hich pulses are generated by the I&F unit 8 is related to the amplitude of the analogue input signal 2. As can be seen trom Equation (1), increasing the amplitude of the analogue input signal, imput, increases the voltage of the output 36 of the comparator 40 at a given point in time; this causes the voltage of the output 36 of the comparator 40 to reach the reference voltage 38 more quickly, and thereby causes a pulse to be generated at the output 10 of the comparator 40 sooner. Thus, each I&F unit 8 getierates more pulses in a given titne period for an analogue input signal 2 of high amplitude than for an analogue input signal 2 of lower amplitude. The number of pulses generated by the I&F unit 8 per unit time may be proportional to the amplitude of the analogue input signal 2, or there may be a non-linear relationship between the number of pulses generated by the I&F unit 8 per unit time and the amplitude of the analogue input signal 2,

The operation of the ADC 1 showm in Fig, 1 will now be described. An analogue input signal 2 is applied to the buffer 4 and distributed to each of the plurality of I&F units 8. Each of the I&F units 8 produces a series of pulses, as previously described, w'hich are collected together at the OR gate 12, Thus, the OR gate 12 produces a pulse whenever any of the l&F units 8 produces a pulse. The counter 16 counts the number of pulses produced by the OR gate and, therefore, counts the total number of pulses produced by all of the I&F units 8. I'hus, the digital wOi'd generated at the output 18 of the counter 16 is a digital representation of the amplitude of the analogue input signal 2 over a given period. For example, wher\ the analogue input signal 2 has a relatively large amplitude during a given period, each of the I&F units 8 wall generate a large number of pulses during that time period and the output 18 of the counter 16 will be a relatively large digital word. On the other hand, if the analogue input signal 2 has a relatively small amplitude during a given period, each of the I&F units 8 will generate fewer pulses during that time period and the output 18 of the counter 16 will be a relatively small digital word.

The output 18 of the counter 16 is fed to the downstream digital system 20 that will make use of the ADC output. The digital system 20 is responsible for resetting the counter 16 periodically by applying an appropriate signal to the reset input of the counter 16. The frequency at which the counter 16 is reset is equal to the sampling frequency of the ADC 1. Thus, an arbitrary sampling frequency can be selected simply by providing reset signals at appropriate inters/als.

For example, if the digital system 20 requires ADC conversions with a sampling rate/(where /is measured in, for example. Hertz or samples per second), the digital system 20 generates a reset signal at a sampling interval of T= Hf (where T is measured in, for example, seconds). The counter 16 counts the number of pulses produced by the I&F units 8 during time T. The number of pulses counted is the result of the analogue to digital conversion i .e. a digital value representing the average value of the analogue input signal 2 during the sampling interval T.

The I&F units 8 are free-running. That is, the I&F units 8 are configured in a certain w^ay when the circuit is initially constructed or tuned and then left to operate independently thereafter. For example, the circuit can be tuned by adjusting the bias input, ib,as, for each I&F unit 8 such an appropriate number of pulses per second are generated for a given analogue input signal, i.nmt·

Fig, 3 is a simplified example which illustrates the w^y in which two I&F units 8a, 8b generate pulses. In this example, the analogue input signal 2 has an average amplitude of VI during the period of time from 0 to T, and an average amplitude of V2 during the period of time from Γιο 2Ί\ where V2 is greater than VI and 7ris the sampling interval. The times at which the first I&F unit 8a generates a pulse are indicated by a dot-dashed line, whilst the times at which the second I&F unit 8b generates a pulse are indicated by a dotted line. The two I&F units 8a, 8b generate pulses at different times. Each I&F unit 8a, 8b generates several pulses throughout each sampling interv^al Γ such that the analogue input signal is effectively sampled at a much greater rate than the sampling rate of the ADC 1 (which, as mentioned above, has a sampling rate off - 1/7). During the first sampling interval (from 0 to Ί), the first I&F unit 8a generates four pulses whilst the second I&F unit 8b generates three pulses. During the second sampling interval (from Γ to 27), the first I&F unit 8a generates eight pulses W'hilst the second I&F unit 8b generates five pulses. This illustrates that a greater number of pulses is generated when the analogue input signal 2 has a larger amplitude. It will be appreciated that similar results will be obtained w'hen a larger number of I&F units are used. The use of more I&F units wall advantageously cause the analogue input signal 2 to be sampled more times during each sampling inteival T, which will provide a more accurate analogue to digital conversion because the noise in the analogue input signal 2 and the noise inherent in the ADC circuit itself w'ill be averaged towards zero by taking a larger number of samples.

The resolution of an ADC is commonly defined as the maximum number of digital values that are used to represent an analogue ir\pui signal, and is mea sured in bits. The reciprocal of the resolution determines the smallest change in the analogue input signal that can be detected by the ADC. The resolution of known .ADCs is fixed. However, the resolution of the ADC disclosed herein is variable, and is a function of the number of I&F units 8, their average pulse rate, and the length of time for which the number of output pulses is counted. The resolution of the ADC described hereii\ is defined as.

(2) where R is the resolution (measured in bits), is the number of I&F units, F is the average pulse rate per I&F unit (measured in pulses per second), and Tis sampling interval (i.e. the period over which pulses are counted, measured in seconds), F is given by the following equation:

(3) wdiere C is the capacitance of the integrating capacitor 32 and Θ is the reference voltage 38 applied to a comparator 40.

The value of F can be determined empirically by measuring the average rate at which pulses are generated for a given analogue input signal, or can be estimated in advance based upon a priori knowledge of the bias current, kias, applied to the I&F units and the expected average amplitude of the input signal, i.„pni.

The resolution R of the ADC disclosed herein can therefore be controlled by the digital system 20, which defines T as explained above. The ability to control the resolution by the digital system 20 provides flexibility to users of the ADC, For example, the resolution of the ADC can be changed simply by modifying software in the digital system, w'ithout the need for any modifications to the hardware in which the ADC is used. From the point of view of a circuit designer, there is a trade-off between the number of I&F units (which adds to circuit complexity and cost) and the rate at which they generate pulses (wftich increases the power consumption); the circuit designer can optimise these parameters according to the requirements of the application in w'hich the ADC is to be used.

The ADC is calibrated in terms of the bias current and threshold. The number of pulses in a time interval At is proportional to At,(h„m.,, -t

For the ADC 1 to operate effectively it is necessary to ensure that the I&F units 8 are not synchronised or, to put this another way, it is necessaiy to ensure that the I&F units generate pulses at different times. If the I&F units 8 were to synchronise they would all sample only a small portion of the analogue input signal 2 around the time at which they all generate pulses, and the signal 2 would not be sampled by any I&F units 8 at other times during the sampling interval T, which would cause the accuracy of the analogue to digital conversion to be less accurate.

There is a risk that that the I&F units 8 might synchronise if the amplitude of the analogue input signal 2 were to increase suddenly to a ver}' large value, which could cause all of the I&F units 8 to produce pulses at approximately the same time. For the ADC 1 to operate optimally, it is necessary to ensure that the I&F units 8 become desynchronised after such an event. Desynchronisation of the I&F units 8 can be achieved by: (i) applying a different bias input, ihias, to each I&F unit 8, such that the outputs of the integrators 30 of each I&F unit 8 drift at different rates; (ii) deliberately adding different noise to each I&F unit 8, such that each I&F unit 8 samples a slightly different signal; (iii) applying a different reference voltage 38 to the comparator 40 of each I&F unit 8, such that each I&F unit 8 creates a pulse at a different value of the analogue input signal 2; (iv) having a different capacitor 32 for each I&F unit 8, such that each integrator 30 integrates the analogue input signal 2 at a different rate; or (v) any appropriate combination of the previously mentioned measures, or any other such means as might be appropriate to the particular implementation. Different reference voltages 38 can be easily provided to each comparator 40 using a resistive potential divider network connected between the power supply and ground, such that each node between twO resistors of the potential divider network is coi\nected to a respective inverting input of a comparator 40, It is not necessary for the components of each i&F unit 8 to have high tolerances, since any variation in the values of the components will advantageously help to achieve the desired effect of avoiding synchronisation of the I&F units 8. For example, if the ADC 1 is fabricated by a silicon process such as a cornplemerttary metal-oxide-semiconductor (CMOS) process, advantageously there may inherently be sufficient process variation in an apparently "identical" set of I&F units 8 to avoid synchronisation of the I&F units 8.

For the purposes of this explanation, it is assumed that the output pulses generated by the comparators 40 are of a sufficiently short duration that there is negligible risk that arty two I&F units' 8 pulses will overlap. In practice, it is possible that two I&F units' pulses will overlap, which will cause the counter 16 to fail to count the later pulse. How'ever, such overlap will not introduce significant errors into the analogue to digital conversion since the failure to count a single pulse is insignificant in comparison with the large number of pulses that are counted during each sampling interval T. All pulses generated by a particular l&F unit 8 have a substantially equal duration, which is determined by inter alia the value of the integrating capacitor 32 and the slew rates of the operational amplifier 31 and comparator 40.

The pulsed outputs tforn the I&F units 8 may be processed in several ways. Whilst the outputs are simply collected together using an OR gate 12 or a circuit 70 having equivalent functionality in the example ADCs described above, the outputs of the I&F units 8 could alternatively (or additionally) be processed using an Address-Event Representation bus (i\ER bus). AER is a protocol that is very w^ll suited to handling data that consists of events, such as the pulses produced by the I&F units 8. Further information on AER can be found in K, .4, Boahen, "Point to Point Connectivity Between Neuromorphic Chips using Address-Events" (IEEE Transactions on Circuits & Systems II, Vol. 47, No. 5, pages 416 to 434, 2000), which is herein incorporated by reference in its entirety. It will also be appreciated that the functionality of an OR gate can easily be implemented using a common-collector, common-emitter or common-gate line in a circuit.

The ADC disclosed herein may be provided in a integrated circuit (IC). The IC is preferably modular, in the sense that it includes input and output pins to allow a plurality of similar ICs to be coupled together in parallel. When coupled together in this way, a first IC would distribute an analogue input signal to the I&F units of one or more similar iCs. The first IC would also receive and count pulses from the I&F units of the other ICs. The modular IC provides a convenient w'ay to increase the number of I&F units present in the ADC, and thereby allows the sampling frequency and resolution to be easily increased.

The ADC disclosed herein has a number of advantages wdth respect to conventional AD(iis, which may give it superior performance in certain applications. These advantages include: i. It is an asynchronous circuit, i.e. it does not require a master clock signal and does not require synchronisation either within its elements or with external circuits. Almost all conventional ikDCs are synchronous, i.e. clocked. It is well known in the ait that synchronous systems are generally more power-consuming than asynchronous systems, because synchronous systems tend to have clock-driven changes of state regardless of whether these are necessary for the operational requirements at any given moment. Additionally, clocked systems require circuitry to generate and distribute the clock signal. Furthermore, the clock frequency is often fixed at the time of manufacture and cannot easily be modified to suit changing purposes or circumstances. By virtue of being an asynchronous circuit, the ADC described herein overcomes or mitigates these problems of synchronous ADCs. ii. It does not require an anti-aliasing circuit. It is w^ell known that correct use of conventional .ADC's requires that the bandwidth of the input signal be reduced to less than half that of the sampling frequency (the Nyquist sampling theorem). This is usually performed by an anti-aliasing filter. Wfith many conventional ADC systems it is necessary to implement this filter using a physical filter circuit prior to the ADC. It is not simple to change the characteristics of this filter after the circuit has been constructed; often it is impossible to change the filter without reconstmcting the circuit. In contrast, the ADC described herein is intrinsically low-pass filtering and so does not require a separate anti-aliasing filter. The ADC described herein is low-pass filtering by virtue of the integration performed by each I&F unit 8 and the averaging of the input signal that occurs from sampling the signal at several diffeient moments in time during each sampling interval 7'by each of the plurality of I&F units 8. The "cutoff frequency" (i.e. the frequency at which the power output of the filter is half the powder in the passband of the filter) of the low-pass filtering performed by the ADC described herein is defined by the rate/at which the counter is reset. To put this another way, the characteristics of the "filter" are defined by the rate at w^ich the counter 16 is sampled. Hence, the characteristics of the "filter" can easily be changed (e g. using appropriate software) by modifying the digital system 20 to reset the counter at a different sampling interv'al T. iii. It is extremely robust to the presence of electrical noise that is inherent in the ADC circuit itself as its operation is inherently by means of integration, integration of the input signal reduces noise because most forms of electrical noise are zero-mean. The effect of noise that is inherent in the circuit itself is largely to improve the desychronisation of the I&F units, since the amplitude of this noise at any point in time will be different for each I&F unit. iv. It is capable of being constructed with very few' transistors, which reduces circuit complexity and cost. V. It can be constiucted to operate using very low voltages, as it may use no more than a single pair of FETs in series betw-een the pow'er supply rails. vi. Its resolution can be easily be varied by resetting the counter 16 at an appropriate interval T, as described above with reference to equation (2). This provides great flexibility. In contrast, most conventional ADCs have a fixed resolution. vii. Its sampling frequency can be easily varied by resetting the counter 16 at an appropriate inters/al T. In contrast, most conventional ADC converters have a fixed sampling frequency, viii. It is capable of sampling very high frequency input signals. The maximum sampling frequency of conventional ADCs is limited by the speed at which their components (e.g. comparators) can respond. In contrast, the use of a plurality of desynchronised I&F units connected in parallel allows the input signal to be sampled at a higher frequency than the components of any single I&F unit would allow. Ii\ the case of the .ADC disclosed herein, the maxiraura frequency of the input signal that can be successfully sampled is determined by the frequency response of the analogue input stages (e.g. the buffer 4 of Fig. 1 and the current mirror circuit 50 of Fig, 2), which can be very high. For example, embodiments of the ADC disclosed herein can successfully sample analogue input signals with frequencies of the order of several gigahertz (i.e. 10® hertz), ix. It does not require a sample and hold circuit. Conventional ADCs require a sample and hold circuit to maintain their input signal at a constant level throughout a sampling interval. In contrast, the operation of the ADC disclosed herein is not adversely affected by changes in the analogue input signal during the sampling interval, and so a sample and hold circuit is unnecessary . This reduces the cost and complexity of the circuit.

It will be understood that the invention has been described above purely by w^y of example, and that modifications of detail can be made within the scope of the invention. In particular, the examples of the invention described above use active-high logic, in which the I&F units generate "high" voltage pulses. It will be understood that the invention also encompasses the use of active-low logic in which the I&F units generate "low'·" voltage pulses and/or in wdiich pulses are collected by a NOR gate and/or in which a counter counts the number of "low^" voltage pulses presented at its input.

Claims

CIAIMS

1. An analogue to digital converter comprising a plurality of circuits each operable to convert an analogue signal into a series of digital pulses, wherein the number of pulses produced by each of the circuits in a particular time period is related to the integral of the amplitude of the analogue signal over that time period, wherein the plurality of circuits are connected in parallel with each other and each comprises an integrator and a comparator, the integrator being arranged to integrate an analogue signal, the integrator having an output coupled to a first input of the comparator, and wherein: each integrator comprises a capacitor, wherein the capacitor of each circuit has a different capacitance value; and/or a different reference voltage is provided to a second input of each comparator.

2. An analogue to digital converter in accordance with claim 1, wdierein the plurality of circuits are configured such that the pulses generated by each circuit are desynchronised with the pulses generated by other circuits. .

3. An analogue to digital converter in accordance claim 1 or claim 2, wherein each of the circuits is configured to generate a respective analogue signal by adding a different bias signal to an analogue input signal.

4. An analogue to digital converter in accordance with any one of the preceding claims, wherein each of the circuits is configured to generate a respective analogue signal by adding a different noise signal to an analo^e input signal.

5. An analogue to digital converter in accordance with any one of the preceding claims, wherein each of the circuits is operable to generate a pulse asynchronously when the integral of the integral of the input signal is equal to a predetermined reference voltage.