GB2542371A

GB2542371A - Communication system

Info

Publication number: GB2542371A
Application number: GB1516429.6A
Authority: GB
Inventors: Lee Jeremy; Robbins David
Original assignee: Thales Holdings UK PLC
Current assignee: Thales Holdings UK PLC
Priority date: 2015-09-16
Filing date: 2015-09-16
Publication date: 2017-03-22
Anticipated expiration: 2035-09-16
Also published as: GB2542371B; GB201516429D0

Abstract

A communications system for transmitting digital audio communication data over a transmission channel (35), the system comprising: a first audio communications unit (or, primary equipment) (31) comprising a clock signal generator (305) operable to define a primary clock signal, and a line encoder (303) operable to encode with run length limited line code, and configured to periodically transmit data on the transmission channel (35), the periodicity (the system heartbeat) being defined by the primary clock signal; a second audio communications unit (or, remote equipment) (33) operable to receive an encoded emission on the transmission channel (35) from the first audio communications unit (31) and comprising: a coarse timing signal extractor operable to extract a coarse timing signal from the periodicity of time of arrival of each packet of data; a first local clock (317) operable to generate a first local clock signal which is adjusted on the basis of the coarse timing signal extracted by the coarse timing signal extractor. The run length limited code may be DC balanced, and may comprise an 8b10b code.

Description

Communication System

FIELD

Embodiments described herein relate to the field of audio transmission, and particularly to digital audio communications systems within commercial aircraft.

BACKGROUND

While the transmission of audio data involves a relatively small amount of data, it presents a particular set of challenges due to the requirement that packets of data arrive in a particular order and at a particular time. Further, any missing data can result in destruction of the audio signal. When the transmission of the audio data is two-way, such as across a telephone line, any latency in the system may negatively impact the user experience.

Audio communication systems within commercial aircraft are subject to particularly stringent latency requirements. For example, the DO-214A aircraft audio systems standard mandates that audio must be available to the recipient within 10ms of entering the system. This ensures that the delay between someone speaking into a microphone and that same speech being received at the load speaker or headset is not so great as to cause noticeable delay to the human ear.

Conventional analogue aircraft communication systems are vulnerable to electromagnetic interference. This is increasingly problematic as the use of mobile phones on commercial aircraft becomes more widespread.

There is a continuing need to develop robust, low-latency audio streaming methods. DESCRPTION OF DRAWINGS

Systems and methods in accordance with non-limiting embodiments will now be described with reference to the accompanying figures, in which:

Figure 1 shows a schematic diagram of a digital audio communication system in accordance with an embodiment;

Figure 2 shows a flow chart of transmission of data in one direction of the digital audio communication system of Figure 1;

Figure 3 shows a flow chart of transmission in the opposite direction of the digital audio communication system of Figure 1;

Figure 4 shows a schematic diagram of clock signals employed in an embodiment;

Figure 5 is a schematic diagram showing coarse adjustment of the clock signals in accordance with an embodiment;

Figure 6 is another schematic diagram showing coarse adjustment of the clock signals in accordance with an embodiment;

Figure 7 is a schematic diagram showing fine adjustment of the clock signals in accordance with an embodiment;

Figure 8 is another schematic diagram showing fine adjustment of the clock signals in accordance with an embodiment;

Figure 9 is a schematic diagram comparing coarse and fine adjustment of the clock signals in accordance with embodiments;

Figure 10 shows a flow chart of fine adjustment of the clock signals in accordance with an embodiment;

Figure 11 shows a schematic diagram of an 8b10b package format; and

Figure 12 shows a detailed schematic diagram of a digital audio communication system in accordance with an embodiment.

DESCRIPTION OF EMBODIMENTS

In an embodiment, a digital audio communications system for transmitting digitised audio data over a transmission channel, the system comprising: a first audio communications unit comprising: a clock signal generator operable to define a primary clock signal; a line encoder operable to encode the digitised audio data into packets of encoded digitised audio data encoded by a run length limited line code; a signal emitter operable to periodically emit, on the transmission channel, a plurality of emissions, each emission comprising a packet of encoded digitised audio data, the periodicity of the emissions being defined by the primary clock signal; a second audio communications unit operable to receive an encoded emission on the transmission channel from the first audio communications unit and comprising: a line decoder operable to extract digitised audio data from a received packet in accordance with the run length limited line code; a coarse timing signal extractor operable to extract a coarse timing signal from the periodicity of time of arrival of each packet of data; a first local clock operable to generate a first local clock signal; and a signal emitter operable to periodically emit, on the transmission channel, a plurality of emissions to the first audio communications unit, the signal emitter being timed by the first local clock signal; wherein the second audio communications unit is operable to adjust the first local clock on the basis of the coarse timing signal extracted by the coarse timing signal extractor.

Such a digital audio communications system allows for a system in which timing data is derived from the audio data itself. The primary clock signal acts as a master clock for the whole system, thereby ensuring synchronisation of data.

The primary clock signal may be a left/right clock signal (LRCLK). The first local clock signal may be a left/right clock signal (LRCLK). Extracting the coarse timing signal from the periodicity of time of arrival of each packet of data may comprise zeroing the LRCLK of the first local clock signal.

The first local clock signal may be a master clock signal (MCLK). Extracting the coarse timing signal from the periodicity of time of arrival of each packet of data may comprise adjusting the MCLK of the first local clock signal.

In an embodiment, the run length limited line code has a run length limit of 5. In a further embodiment, the run length limited line code is DC balanced. In yet a further embodiment, the primary clock signal and the local clock signal are single phase clock signals.

Such run length limited line codes enable straightforward detection the commencement of transmitted data packets. They also provide frequent edge transitions which enable regular synchronisation across the communication system.

The run length limited line code may be an 8b10b code. The 8b/10b code may define at least one reserved code character. The signal emitter of the first audio communications unit may be operable to precede each emitted packet by at this reserved code character. The reserved code character may be K28.5. The system may derive the coarse timing signal from the transition between the reserved code character and data characters in an 8b10b code.

In an embodiment the digital audio communication system further comprises a second local clock operable to generate a second local clock signal; and a fine timing signal extractor operable to determine a fine timing signal from signal transition edges of the second local clock signal, and to use the fine timing signal to adjust the first local clock accordingly.

The fine timing signal extractor may be operable to adjust the first local clock by delaying the coarse adjustment to the first local clock until the second local signal has generated a predetermined number of edges.

The first local clock signal may be a LRCLK signal and the second local clock signal may be a master clock signal (MCLK). The fine timing signal may be operable to adjust a LRCLK signal. The fine timing signal may be operable to adjust the LRCLK signal by delaying zeroing of the LRCLK until an expected number of MCLK edges have been observed.

The coarse timing signal may also adjust the MCLK. The coarse timing signal may adjust the MCLK and the LRCLK simultaneously. The coarse timing signal may adjust the MCLK immediately but the adjustment to the LRCLK may be delayed by the fine timing signal. Zeroing of the LRCLK may be delayed until the expected number of MCLK edges following adjustment of the MCLK have been observed.

In an embodiment, a method of transmitting digitised audio data over a transmission channel, the method comprising, in a first audio communications unit: generating a clock signal to define a primary clock signal, encoding the digitised audio data into packets of encoded digitised audio data encoded by a run length limited line code, periodically emitting, on the transmission channel, a plurality of emissions, each emission comprising a packet of encoded digitised audio data, and timing the periodicity of the emissions using the primary clock signal; and in a second audio communications unit: receiving an encoded emission on the transmission channel from the first audio communications unit, generating a first local clock signal, extracting digitised audio data from a received packet in accordance with the run length limited line code, extracting a coarse timing signal from the periodicity of time of arrival of each packet of data, adjusting the first local clock on the basis of the coarse timing signal extracted by the coarse timing signal extractor, periodically emitting, on the transmission channel, a plurality of emissions to the first audio communications unit, and timing the periodicity of the emissions using the first local clock signal.

In an embodiment, the method further includes DC balancing the run length limited line code. The wherein the run length limited line code may be an 8b10b code. At least one reserved code character in the 8b10b code may be defined and at least one reserved code character emitting prior to emitting each packet.

The method may further comprise generating a second local clock signal; determining a fine timing signal from signal transition edges of the second local clock signal, and adjusting the first local clock accordingly. Adjusting the first local clock may comprise delaying the coarse adjustment to the first local clock until the second local signal has generated a predetermined number of edges.

Figure 1 shows a crude schematic diagram of a digital audio communication system according to an embodiment. The system comprises primary equipment 31 and remote equipment 33 which is physically remote from primary equipment 31. The system is configured to transmit digital audio data from the primary equipment 31 to the remote equipment 33 and vice versa. Both the primary equipment 31 and the remote equipment 33 comprise a number of modules. Note that the components of the schematic diagram of figure 1 are intended to emphasise the functionality provided within the communication system and not necessarily to correspond to actual components present in the system. For example, the functions provided by the modules described below may be provided by more than one component. Likewise, more than one function may be combined within a single component. An example of one detailed implementation of this embodiment will be described below.

Both sets of equipment comprise an audio input 301 for inputting audio for transmission between the primary equipment and the remote equipment. This may comprise a microphone, a memory, a memory storage device or the like. Both sets of equipment also comprise an output 319. The output 319 may comprise a speaker, a headset, a memory file or a data storage device or the like.

Audio data which is input into either equipment is encoded as digitised run length limited line code by an encoder module 303. The significance of the limited run length of the line code will become apparent below. A transmitter module 307 then transmits the line code periodically to the other equipment along a transmission channel 35 whereby it is received by receiver 309. The precise, periodic transmissions are known as the system “heartbeat”; a new signal is transmitted on each heartbeat. The received signals are decoded by decoders 303 and audio data is output from output model 319.

The periodicity of the signal transmission from transmitters 307 are determined by clock modules 305 and 317 comprised in the primary equipment 31 and remote equipment 33 respectively. These clock modules also providing clocking for the encoder 303 and decoder 321 of their respective equipment. Examples of the clocking requirements of these modules according to embodiments will be further described below.

The primary equipment clock module 305 remains unadjusted throughout operation of the system.

In contrast, the remote equipment clock module 317 is adjusted by adjustment module 315 according to the periodicity of the data received at the remote equipment 33 from the primary equipment 31. The encoding used in the system provides for commencement of new packets of information at regular intervals. This provides a “heartbeat” which can be used by recipient devices for clock synchronisation purposes.

Coupled with this is an arrangement whereby, in order to complete a packet to the regulated length, a sequence of “null” characters (otherwise unused characters of the line code) are inserted to time. The commencement of a packet can thus be easily determined from the transition from null characters to valid characters of the line code character set.

On top of this, the structure of the line code characters provides a further timing opportunity. That is, by defining the line code as a run length limited line code, the encoded data will produce frequent edge transitions - the number of bits of coded data of the same value that can appear on the line consecutively is limited. Therefore, edges will be encountered to enable further synchronisation.

The adjustment module detects transitions and adjusts the remote equipment clock 317 so as to be synchronised with them. Thus, the remote equipment clock 317 is continually adjusted in real time to ensure correct alignment of the audio data at both ends of the system. There is no separate clock line in the system; all timing data is derived from the audio data itself. This enables the provision of an audio transmission system with a simple, compact, low-power design while maintaining excellent sound quality and minimising latency. A detailed description of the remote equipment clock adjustment according to embodiments will be given below.

Figure 2 shows a flow chart of the process of transmitting data from the primary equipment 31 to the remote equipment 33.

In step S201, audio data is input into the primary equipment. In Step S203, the input audio data is encoded as limited line length code. In step S205, the encoded audio data is transmitted such that a packet of data is transmitted every heartbeat, as determined by the primary equipment clock. In step S207 the packets of data are received at the remote equipment. As they are received, the clock adjustment module detects the transition from null data characters to valid data characters signifying the start of a new packet of data and also edge transitions within the data packet. In step S209, the clock adjustment module adjusts the remote equipment clock accordingly so that it is synchronised to the incoming data. In step S211, the received data is decoded. The decoder is clocked by the adjusted clock module. In step S213 the decoded audio data is output.

Figure 3 shows a flow chart of the process of transmitting data in the opposite direction, that is, from the remote equipment 33 to the primary equipment 31. In step 301, audio data is input into the remote equipment. In Step S303, the input audio data is encoded as limited line length code. In step S305, the encoded audio data is transmitted such that a packet of data is transmitted every heartbeat. In this case the heartbeat is determined by the remote equipment clock. However, as the remote equipment clock is synchronised to data received from the primary equipment, the periodicity of the heartbeat and therefore transmission of the packets of digitised audio data is the same as that as determined by the primary equipment clock. In step 3207 the packets of data are received at the remote equipment. Thus, steps S301 to S307 proceed analogously to S201 to S207 with the only difference being that the data is input to and transmitted from the remote equipment.

In contrast to the process of Figure 2, however, there is no adjustment of the primary equipment clock following the receiving of data from the remote equipment. Instead, the process proceeds straight to S311 in which the audio data is decoded. In step S313 the audio data is output from the primary equipment.

In an embodiment, two audio channels are transmitted between the remote equipment and the primary equipment. However, in other embodiments, more than two channels may be transmitted.

In this embodiment, both audio channels are transmitted as a single serial stream; data corresponding to each channel is transmitted sequentially.

In this embodiment, each clock provides at least two clock signals: a faster, master clock signal (MCLK) and a slower left/right clock signal (LRCLK). The MCLK provides overall synchronization for its respective equipment. The LRCLK provides the synchronisation of the two audio channels. The value of the clock signal determines whether the encoder 303 encodes data from the left channel or the right channel into the serial line code. Likewise, the value of the clock signal determines whether the decoder 321 processes the data to be decoded as left channel or right channel data.

Synchronisation of the LRCLK in the remote equipment with the LRCLK in the primary equipment is therefore necessary to ensure that the audio data is correctly aligned upon output. A schematic diagram showing the LRCLK 401 and the MCLK 407 is shown in Figure 4. When the LRCLK is low 403 the data stream is processed as left channel data. When the LRCLK is high 405 the data stream is processed as right channel data. Note that the LRCLK 401 is itself synchronised with the MCLK 407 as the MCLK provides the master timing reference for all processes within each piece of equipment.

In an embodiment, the adjustment performed by the clock adjustment module 315 is a “coarse” adjustment and involves adjusting the LRCLK and MCLK together in accordance with the received data signal. Two examples of this are shown in Figures 5 and 6. The clock signal proceeds as in Figure 4 until time t. At time t, a heartbeat 501, that is, a transition from a null character to a valid character in the data received from the primary equipment, is detected by the clock adjustment module. The clock adjustment module zeroes the MCLK and LRCLK signals accordingly.

In the embodiment of Figures 5 and 6, the MCLK is adjusted so that a clock edge is synchronised with the heartbeat. If the MCLK is low when the heartbeat arrives, an upward clock edge is aligned with the heartbeat, as in Figure 6. If the MCLK is high when the heartbeat arrives, however, a downward clock edge is aligned with the heartbeat, as in Figure 5. The solid lines indicate the actual clock signal. The dashed lines 503 indicate the value the clock signal would have had without adjustment.

The LRCLK is also zeroed at the heartbeat. The next LRCLK following zeroing will therefore be seen when number of MCLK clock edges following normal (i.e. non-adjusted zeroing of the LRCLK) have been seen. In other words, when a heartbeat arrives, the clock counter is cleared, effectively adjusting the start of the MCLK and LRCLK. This can be seen in Figures 5 and 6.

In another embodiment, the clock adjustment module also performs a fine adjustment in addition to the coarse adjustment described above. In practice, the fine adjustment comprises delaying the coarse adjustment of the LRCLK until the correct number of MCLK edges have occurred. Figures 7 and 8 show examples of adjustment of the clock lines in which there is a fine adjustment in addition to the coarse adjustment.

In this embodiment, the MCLK is adjusted so that a clock edge is synchronised with the heartbeat. As in Figures 5 and 6, if the MCLK is low when the heartbeat arrives, an upward clock edge is aligned with the heartbeat. If the MCLK is high when the heartbeat arrives, however, a downward clock edge is aligned with the heartbeat. Adjustment of the LRCLK is performed when the expected number of MCLK edges has occurred. In practice this means the number of MCLK edges that would have occurred before a LRCLK edge was seen if the clock signal had not been adjusted. Unlike embodiments in which only coarse adjustment is performed, therefore, the clock counter is not cleared upon arrival of the heartbeat.

Figure 9 shows an embodiment in which only a course adjustment is performed (a) and an embodiment in which a fine and coarse adjustment is performed (b) but wherein the heartbeat is received at the same time. This is to enable comparison between the fine and coarse adjustments.

Figure 10 shows a flow chart which demonstrates the process of fine adjustment. In step S1001, the transition between the null characters and valid characters, i.e. the heartbeat is detected by the adjustment module. In step S1002, the MCLK is adjusted in accordance with this received heartbeat, as described above. In step S1003, the adjustment module detects the number of edges of the adjusted MCLK. In step S1004, once the appropriate number of edges has been detected, the clock adjustment module adjusts the LRCLK.

Thus, in this embodiment, there is no requirement for a separate clock line synchronisation to be performed; the two systems are synchronised in real time using the audio data itself. This is done in an optimal way because every data transmission carries useful data both for audio and for synchronisation of the audio channels. Systems according to this embodiment therefore experience minimal latency and buffering at all stages is limited.

In an embodiment, the limited length line code has 8b10b format. 8b10b has a run length limit of 5 and 32 bytes of data are transmitted with each package. Full details of the 8b10b format can be found in IBM J. Res. Develop., Vol. 27, No. 5. A schematic diagram of the 8b10b package format is shown in Figure 2. Each message comprises a simple address portion 21 which enables different types of messages to be differentiated. In an embodiment, both audio messages 23 and configuration messages 25 are transmitted between the master and remote equipment. The role of configuration data in the communication system will be described in more detail below. The address portion of the frame 21 distinguishes between the two types of messages. Each message also comprises the audio 27 or configuration data 29 portion and a cyclic redundancy check portion 31 which enables checking of the transmitted data.

Note that the package format is the same in both the transmit and receive directions.

In the 8b10b scheme, the null character 31 employed between packets of data is K28.5. Thus, the heartbeat adjustment module detects the transition from a K28.5 character to the address portion of the packet 21. 8b10b has a number of advantages over other digital protocols for use in audio transmission systems. Firstly, it employs a single phase embedded clock which requires a maximum of 1 transition per data bit. This permits a low drive strength, long data runs, inexpensive drivers. It is also robust. In addition, relatively few transmissions are required for each amount of data. 8b10b is also DC-balanced meaning that it is suitable for use in power over data implementations. For example, in the embodiment of Figure 1, power to the remote equipment may be provided from the primary equipment via the transmission channels 35. This is advantageous in aircraft where it is preferable not to have an additional on board power source for the remote equipment.

Finally, 8b10b coding scheme also allows clock recovery without double-rate data transitions which enables more than two audio channels to be transmitted as a single stream with minimal bandwidth.

Figure 12 shows a detailed schematic diagram of a digital audio communication system in accordance with the embodiment of figure 1. The system comprises primary equipment 11 and remote equipment 13 which is physically remote from the master equipment 11. The system is configured to transmit audio data both ways between the master equipment 11 and the remote equipment 13. The master equipment and the remote equipment are connected by data links 15. In an embodiment, the data links comprise an unshielded twisted pair cable. In an embodiment, the data links comprise Category 5 unshielded twisted pair cable.

In this embodiment, the master equipment 11 comprises a printed circuit board which itself comprises a codec 19, a codec reference clock module 101 and an audio management central processing unit 103. The codec encodes audio data received via an input from a microphone or a headset into a digital stream of data. The codec also decodes digital audio data for output via the speaker or headset. The codec reference clock module 101 provides a timing reference to the codec 19 and the audio management central processing unit (CPU) 103. The audio management CPU 203 controls the movement of codec data samples between the codec and a field programmable gate array (FPGA) comprised within the master equipment. The timing of this movement is governed by the codec reference clock. The samples move from the codec to the FPGA (and vice versa) as a serial I2S data stream. The I2S standard is well known in the art.

The master equipment FPGA comprises an audio management port 105 via which audio data are transferred to and from the master equipment CPU. The FPGA further comprises two sets of audio buffers 109 and 113; one for outgoing audio data and one for incoming audio data. In this embodiment, the buffers are First In First Out (FIFO) buffers. Audio data are transferred from the audio management port 105 to the outgoing audio buffers 109. Likewise, audio is transferred from the ingoing audio buffers 113 to the audio management port 105.

The FPGA further comprises a transmitter 111 which is configured to transmit 8b10b line code. Audio samples are extracted from the outgoing buffers 109 and packaged into 32 byte messages. The messages are then transmitted serially to the remote equipment via the twisted pair cable 15 such that there is a new message transmitted every heartbeat. In this embodiment the audio message transmission interval is 500pS. The transmission interval is precisely controlled by a heartbeat management module 107 which itself receives timing data from the codec reference clock 101.

The primary equipment FPGA further comprises a receiver 115 which receives 8b10b line code from the remote equipment 13 and decodes it back into data bytes. The contents of the de-framed data is written to the incoming data buffers 113 before being extracted by the audio management port 105. The receiver is clocked by a local clock management module 117 which is independent from the codec reference clock 101. This clock is also adjusted when the heartbeat is received, thereby insuring synchronisation with the codec reference clock 101.

The remote equipment 13 comprises a printed circuit board which itself comprises a codec 135. A codec controller 133 controls the movement of data between the codec and remote equipment FPGA. The timing of this movement is controlled by a local clock management module 129.

As with the primary equipment, the FPGA comprises two sets of audio buffers 125 and 133; one for outgoing audio data and one for incoming audio data. Audio data are transferred from the codec controller to the outgoing audio buffers 133. Likewise, audio is transferred from the ingoing audio buffers 125 to the codec controller 133.

The remote equipment codec 135 sends a continuous serial stream of audio samples to the remote equipment FPGA via an I2S interface, which is transposed back into bytes before being written to the outgoing buffers 133. As in the primary equipment, the FPGA comprises a transmitter 119 which is configured to transmit 8b10b line code. Audio samples are extracted from the outgoing buffers 133 and framed up into 32 byte messages. The messages are then transmitted serially to the remote equipment via the twisted pair cable 8b10b link with a new message being transmitted on every heartbeat.

In contrast to the primary equipment, in the remote equipment, the timing of the heartbeat for transmission of data is not determined by a local clock but is instead recovered directly from data received from the primary equipment.

As in the primary equipment, the remote equipment FPGA comprises a receiver 121 which receives 8b10b line code from the primary equipment 11. This received data is written to the incoming data buffers 125 before being extracted by the codec controller 133. The codec controller is clocked by a local clock management module 129.

Unlike the primary equipment, however, the remote equipment FPGA additionally comprises a heartbeat recovery module 123 which detects the heartbeat from the incoming data received at the receiver 121, as described above in relation to Figure 1. This recovered heartbeat is then used as the timing reference for transmission of data from the remote equipment transmitter 119. Note that the regenerated heartbeat itself does not undergo fine adjustment, only the Codec clocks.

When the audio messages received at the primary equipment are written to the FPGA incoming buffers 113 as described above, the regeneration of the heartbeat ensures that the audio samples will be available to be read by the primary equipment audio management block and will remain synchronised to the primary equipment codec reference clock.

The synchronisation of the two clocking systems in this way ensures that audio integrity is maintained throughout the system while optimising the audio buffer depth of the audio FIFOs and minimising latency.

The regenerated audio heartbeat is also used as the timing reference to extract audio samples from the remote equipment incoming buffers 125 and supply them to the remote equipment codec 135 as an I2S data stream at the correct time. The heartbeat recovery module 123 provides a timing reference to the master clock fine adjustment module 131 which in turn provides a timing reference to the codec controller 133. The local clock management module 129 is a free running clock and is not adjusted by the heartbeat as precise synchronisation is not required. The codec controller then controls the timing of the codec and the movement of audio data between the buffers and the codec according to the local clock.

Finally, the remote equipment FPGA comprises configuration registers 127. When configuration data is received at the remote equipment, this is extracted by the configuration registers from the buffers 125 and is used to set the registers in the configuration memory.

The system shown Figure 12 does not require any microprocessor control in the remote equipment, nor additional and complex logic or IP blocks to manage the data/audio stream; all the information necessary for alignment of the audio data is extracted, in real time from audio data received from the primary equipment. This enables a low-power system due to its simple, compact design and lack of additional components. This in turn permits power-over data transmission reducing the need for additional power sources and allowing such systems to be implemented at low cost.

Systems in accordance with the above embodiments enable robust, low latency, audio streaming. Indeed, latency in systems according to the above embodiments has been shown to be compliant with the DO-214A aircraft audio systems standard. Such implementations allow two remote audio systems to operate without sample errors and maintain the synchronisation of their respective Codecs.

In addition to aircraft, systems in accordance with the above embodiments are suitable for use in any vehicles operating in high-noise environments.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

CLAIMS:

1. A digital audio communications system for transmitting digitised audio data over a transmission channel, the system comprising: a first audio communications unit comprising: a clock signal generator operable to define a primary clock signal; a line encoder operable to encode digitised audio data into packets of encoded digitised audio data encoded by a run length limited line code; a signal emitter operable to periodically emit, on the transmission channel, a plurality of emissions, each emission comprising a packet of encoded digitised audio data, the periodicity of the emissions being defined by the primary clock signal; a second audio communications unit operable to receive an encoded emission on the transmission channel from the first audio communications unit and comprising: a line decoder operable to extract digitised audio data from a received packet in accordance with the run length limited line code; a coarse timing signal extractor operable to extract a coarse timing signal from the periodicity of time of arrival of each packet of data; a first local clock operable to generate a first local clock signal; and a signal emitter operable to periodically emit, on the transmission channel, a plurality of emissions to the first audio communications unit, the signal emitter being timed by the first local clock signal; wherein the second audio communications unit is operable to adjust the first local clock on the basis of the coarse timing signal extracted by the coarse timing signal extractor.

2. The digital audio communications system of claim 1, wherein the run length limited line code has a run length limit of 5.

3. The digital audio communications system of claim 1, wherein the run length limited line code is DC balanced.

4. The digital audio communications system of claim 1, wherein the primary clock signal and the local clock signal are single phase clock signals.

5. The digital audio communications system of claim 1, wherein the run length limited line code is an 8b10b code.

6. The digital audio communications system of claim 5, wherein the 8b10b code defines at least one reserved code character and wherein the signal emitter of the first audio communications unit is operable to precede each emitted packet by at least one emission of a reserved code character.

7. The digital audio communication system of claim 1, further comprising a second local clock operable to generate a second local clock signal; and a fine timing signal extractor operable to determine a fine timing signal from signal transition edges of the second local clock signal, and to use the fine timing signal to adjust the first local clock accordingly.

8. The digital audio communication system of claim 7, wherein the fine timing signal extractor is operable to adjust the first local clock by delaying the adjustment to the first local clock on the basis of the coarse timing signal until the second local signal has generated a predetermined number of edges.

9. A method of transmitting digitised audio data over a transmission channel, the method comprising, in a first audio communications unit: generating a clock signal to define a primary clock signal, encoding the digitised audio data into packets of encoded digitised audio data encoded by a run length limited line code, periodically emitting, on the transmission channel, a plurality of emissions, each emission comprising a packet of encoded digitised audio data, and timing the periodicity of the emissions using the primary clock signal; and in a second audio communications unit: receiving an encoded emission on the transmission channel from the first audio communications unit, generating a first local clock signal, extracting digitised audio data from a received packet in accordance with the run length limited line code, extracting a coarse timing signal from the periodicity of time of arrival of each packet of data, adjusting the first local clock on the basis of the coarse timing signal extracted by the coarse timing signal extractor, periodically emitting, on the transmission channel, a plurality of emissions to the first audio communications unit, and timing the periodicity of the emissions using the first local clock signal.

10. The method of claim 9, further comprising: DC balancing the run length limited line code.

11. The method of claim 9, wherein the run length limited line code is an 8b10b code.

12. The method of claim 11, further comprising: defining at least one reserved code character in the 8b10b code; and emitting at least one reserved code character prior to emitting each packet.

13. The method of claim 9, further comprising: generating a second local clock signal; determining a fine timing signal from signal transition edges of the second local clock signal, and adjusting the first local clock accordingly.

14. The method of claim 13, wherein adjusting the first local clock comprises delaying the adjustment to the first local clock on the basis of the coarse timing signal until the second local signal has generated a predetermined number of edges.