GB2539925A

GB2539925A - DC free line coding robust against transmission error

Info

Publication number: GB2539925A
Application number: GB1511529.8A
Authority: GB
Inventors: Achir Mounir
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2015-07-01
Filing date: 2015-07-01
Publication date: 2017-01-04
Anticipated expiration: 2035-07-01
Also published as: GB2539925B; GB201511529D0

Abstract

A method of processing a bitstream comprising a plurality of encoded codewords, the method comprising: obtaining an encoded codeword comprising a plurality of bits, each of the plurality of bits being associated with a bit position in the codeword; obtaining a puncturing code designating bit-positions of the codeword to be punctured prior to decoding; obtaining a modified codeword by modifying at least one bit of codeword at a bit-position designated by the puncturing code in order to keep the value of a Running Digital Sum (RDS) and/or a Running Alternate Sum (RAS) bounded. Embodiments make it possible to attain improved performances in terms of BER (bit error ratio).

Description

DC FREE LINE CODING ROBUST AGAINST TRANSMISSION ERROR

FIELD OF THE INVENTION

The present invention relates to DC free line coding and a method of using error correction coding to facilitate DC balance after transmission on a noisy communication channel. The application is particularly relevant for wireless communications.

BACKGROUND OF THE INVENTION

In the prior art, lines codes are used for shaping the spectrum of a bitstream when transmitted into a communication medium. For example, the 8B10B line coding is used to remove the DC components (thus referred to as DC-free code) so that the spectrum of the bitstream has no power at the null frequency. For some systems it is essential to have a DC free bitsream since generally the null frequency is filtered by the decoupling capacitors that are used between the different stages of the transceivers (filters, amplifiers ...etc.). Lines codes may also be used to have Nyquist-free bitstream (null power at the Nyquist frequency). Also, a combination of a line coding with an error correction coding (ECC) is commonly used in order to have both error correction and DC free capabilities.

One of the most popular line coding schemes is the 8B10B code which encodes each 8 bits into 10 bits and a status information obtained from the previous encoding. The idea is to balance continuously between the ones and the zeros so that at each time the encoded bitstream has exactly the same number of ones and the number of zeros and hence the bitstream is DC free. The DC free encoding modifies the inputted bitstream into an output bitstream having a bounded digital sum variation. The digital sum variation (DSV) is computed from the running digital sum (RDS) as follows (after modulating the bitstream with 1 and -1):

And the digital sum variation is computed by the following formula:

For the encoding, the data is divided into blocks of 8 bits (one byte) and presented to the encoder. Each byte is then divided into two sub-blocks; first five bits and last three bits. The first five bits are encoded by a 5b/6b code to obtain 6 bits. The last three bits are encoded by a 3b/4b code to obtain 4 bits. The total number of bits of the encoded word being 10.

The 5b/6b encoding is based on two tables; a first table contains codewords having more ones than zeros (or the same number of ones and zeros for some codewords in the table) and a second table containing codewords having more zeros than ones (or the same number of ones and zeros for some codewords in the table).

The tables used for the 5b/6b encoding are listed below. In the table “table_5b_6b_RD_plus”, codewords have a number of zeros at least equal to the number of ones. And in the table “table_5b_6b_RD_minus”, codewords have a number of ones at least equal to the number of zeros. table_5b_6b_RD_plus =[0 1 1 000; 1 000 1 0; 0 10010; 1 1 000 1; 001010; 10 1001; 0 11001; 000 1 1 1; 0 0 0 1 1 0; 100101; 0 10 10 1; 110 10 0; 001101; 10 110 0; 0 1110 0; 1 0 1 0 0 0; 1 0 0 1 0 0; 1 000 1 1; 0 10011; 110 0 10; 001011; 10 10 10; 0 110 10; 000 1 0 1; 00 1 1 00; 100110; 0 10 110; 00 1 00 1; 001110; 0 1 000 1; 1 0000 1; 0 10 10 0]; table_5b_6b_RD_minus = [1 0 0 1 1 1; 0 1110 1; 10 110 1; 1 1 000 1; 110 10 1; 10 1001; 0 11001; 1 1 1 0 0 0; 111001; 100101; 0 10 10 1; 110 10 0; 001101; 10 110 0; 0 1110 0; 0 10 111; 0 110 11; 1 000 1 1; 0 10 0 11; 110 0 10; 001011; 10 10 10; 0 110 10; 1110 10; 110 0 11; 10 0 110; 0 10 110; 110 110; 0 0 1110; 10 1110; 0 11110; 10 10 11];

The tables used for the 3b/4b encoding are listed below. In the table “table_3b_4b_RD_plus”, codewords have a number of zeros at least equal to the number of ones. And in the table “table_3b_4b_RD_minus”, codewords have a number of ones at least equal to the number of zeros. table_3b_4b_RD_plus = [0100; 100 1; 0 10 1; 00 11; 00 10; 10 10; 0 110; 000 1; 1 0 0 0]; table_3b_4b_RD_minus = [1 0 1 1; 100 1; 0 10 1; 110 0; 110 1; 10 10; 0 110; 1110; 0 111];

Example:

Let’s consider the encoding of the following byte: 00001 001. The encoded word would be: 01 1000101 1 when the initial running disparity is equal: +1; 1001110100 when the initial running disparity is equal: -1.

If the running disparity (i.e. number of ones minus the number of zeros for each encoded 6 bits or 4 bits at the output of resp. the 5b/6b and 3b/4b encoders) is equal to +1, the byte to be encoded (i.e. 00001 001; see the example above) is divided into two parts: five first bits (i.e. 0 0 0 0 1) and three last bits (i.e. 0 0 1). As the running disparity is equal to +1 then the 5b/6b encodes the five first bits with: 0 110 0 0 (since 0 0 0 0 1 corresponds to 1 in decimal so the first word in the table is selected as 5b/6b codeword) hence the new running disparity will be equal to: +1 + (2 - 4) = -1; +1 represents the previous/initial running disparity and (2 - 4) is the running disparity of the encoded word (0 1 1 000). As the updated running disparity is equal to -1 hence the table table_3b_4b_RD_minus is used for the 3b/4b encoding. The output is equal to: 1 0 1 1. For each byte to be encoded two codewords are possible (positive or negative running disparity).

Other codes are proposed in the prior art dealing with the DC free or DC free and Nyquist free characteristics. The code proposed in M-C. Chiu uses the convolutional codes to build a DC free error correcting code. This code is constructed by preforming a XOR operation between two convolutional codes. This is a linear combination of these two codes.

The first convolutional code is used in order to encode the uncoded sequence. Let’s consider a(D) as the source input (represented in the polynomial format), x(d) be the encoded sequence and G1(D) the polynomial generator matrix of the first convolutional code. The first operation is to perform the encoding : x(D) = a(D). G1(D). A second step is to perform a second encoding based on a second convolutional code. In this second step, the Viterbi algorithm is performed on the trellis of the second convolutional code in order to find a codeword b(D) (b(D) is a codeword belonging to the second convolutional code codebook). The codeword b(D) is then added to the codeword x(D) : y(D) = x(D) + b(D) = a(D) G1(D) + u(D) G2(D) = [a(D) u(D)] . [G1(D) G2(D)f

At the decoder side the classical Viterbi Algorithm is applied on the received sequence by using the trellis of the following code: G(D) = [G1(D) G2(D)]^. This method to generate a DC free Error Code can be applied with many convolutional codes. Of course the performances depends on the characteristics of the selected convolutional codes. A list of preferable convolutional codes, for both C1 and C2, is disclosed in M-C. Chiu in two tables (Chiu - “DC Free Error Correcting Codes Based on Convolutional Codes”, IEEE Transaction on Communications, Vol. 49, N. 4, April 2001).

The code proposed in J. G. Kim [ “An improved DC free Nyquist free Error Control Line Code”, ICCS’94, November 1994] uses the extended hamming code to build a DC free error correcting code. The (8,4) extended hamming code has some interesting characteristics since 12 among 16 of the codebook codewords have a null running digital sum and a null alternate digital sum as shown in the table below.

Extended Hamming encoding tabie (with DS and AS vaiues)

In J. G. Kim, the idea is to build a new code starting from a part of the codewords listed in the table 5. Indeed, twelve of these codewords have a null DS and a null AS hence a table containing 144 codewords of 16 bits can be constructed by concatenating two by two the codewords of the table 5. This new table contains 144 codewords of 16bits each one having a null running digital sum and a null running alternate sum. A third table is obtained by selecting only 128 codewords out of 144 codewords of the second table. With this third table having 128 codewords, one can encode one seven bits word to 16 bits codeword belonging to the third table (since 2^ = 128). The coding rate that is obtained is 7/16 = 0.4375.

Despite the above encoding techniques there is still a need for enhanced encoding capabilities with DC free line code. The present invention lies within this context.

SUMMARY OF INVENTION

It is a broad objective of the proposed present invention to generate a DC free line code with error correction capabilities.

According to a first aspect of the invention there is provided a method of processing a bitstream comprising a plurality of encoded codewords, the method comprising: obtaining an encoded codeword comprising a plurality of bits, each of the plurality of bits being associated with a bit position in the codeword; obtaining a puncturing code designating bit-positions of the codeword to be punctured prior to decoding; obtaining a modified codeword by modifying at least one bit of codeword at a bit-position designated by the puncturing code in order to keep the value of a digital sum (RDS) and/or a running alternate sum (RAS) bounded.

Embodiments make it possible to attain improved performances in terms of BER (bit error ratio). Also, embodiments may be implemented in a non-complex fashion at en coders and decodes. Advantageously, DC free and/or Nyquist free output bitstreams are obtained.

The method may further comprise a step of determining if modification of the codeword is needed, the said step comprising checking if the value of digital sum (RDS) and/or a running alternate sum (RAS) of the codeword is not bounded.

The method may further comprise a step of transmitting the modified codeword.

For example, the puncturing code is based at least in part on a measure of channel quality.

According to embodiments, the measure of channel quality is a measured signal to noise ratio.

For example, the puncturing code is obtained independently at a transmitting device modifying the codeword and at a receiving device receiving the modified codeword.

According to embodiments, the puncturing code is communicated from a transmitting device modifying the codeword to a receiving device receiving the modified codeword.

According to embodiments, the puncturing code is based at least in part on the minimum number of bits that need to be modified to reach a DC-free state and/or a Nyquist-free state.

The method may further comprise receiving the modified codeword at a receiving device and puncturing the received modified codeword at the at least one bit-position designated by the puncturing code.

For example, the encoded codeword is obtained by performing an error correction coding.

The method may further comprise transmitting the encoded codeword, and the error correction coding may be a punctured convolution coding and no puncturing may be performed before transmission.

According to a second aspect of the invention there is provided a device for processing a bitstream according to the first aspect.

According to a third aspect of the invention there is provided a device for generating encoded codewords of a bitstream and for processing the bitstream according to the first aspect.

According to a fourth aspect of the invention there is provided a device for decoding a bitstream generated by an encoding device according to the third aspect.

According to a fifth aspect of the invention there is provided a system comprising; - an encoding device according to the third aspect, and - a decoding device according to the fourth aspect.

The is also provided a non-transitory information storage means readable by a computer or a microprocessor storing instructions of a computer program, for implementing a method according to the first aspect of the invention, when the program is loaded and executed by the computer or microprocessor.

The objects according to the second to fifth aspects of the invention provide at least the same advantages as those provided by the method according to the first aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the present invention will become apparent to those skilled in the art upon examination of the drawings and detailed description. Embodiments of the invention will now be described, by way of example only, and with reference to the following drawings.

Figure 1 illustrates an encoder (Forward Error Correction and DC free block code).

Figure 2 illustrates an example of a convolutional code encoder and the associated trellis.

Figure 3 illustrates an encoding algorithm (DC free convolutional code). Figure 4 illustrates a spectrum of the DC free bitstream obtained according to embodiments.

Figure 5 illustrates an adaptive re-encoding algorithm with the SNR criterion.

Figure 5 bis illustrates an adaptive re-encoding algorithm with the RDS criterion.

Figure 6 illustrates simulation results plotting the BER comparison for (K1,N1)=(1,6) and (K2,N2)=(1,3).

Figure 7 illustrates a decoding algorithm.

Figure 8 illustrates a branch metric computation for the decoding algorithm.

Figure 9 illustrates an optimal decoding algorithm.

Figure 10 schematically illustrates a general architecture of a device according to embodiments.

DETAILED DESCRIPTION

The invention will now be described by means of specific non-limiting exemplary embodiments and by reference to the figures.

In all the figures of the present document, the identical elements and steps are designated by a same numerical reference.

In the present invention, a DC free Error correction code is constructed from the standard convolutional code. The use of the classical puncturing code, applied to the convolutional code, permits to balance the RDS value and hence remove the DC component of the power spectrum of the encoded bitstream. In the present invention, any classical convolutional code decoder can be used without any modification. Any convolutional code can be used.

Figure 1 represents an example of the architecture of an exemplary encoder. The encoder 110 is comprised of a Forward Error Correction (101) concatenated with a DC free block code (102); like for example: 8B10B, MB810 ...etc. The Forward Error Correction could be any known code.

For the case of the Convolutional code, a table containing some possible convolutional codes with the optimum constraint length having coding rates equal to 1/2 and 1/3 is available in Bernard Sklar ‘Digital Commuications’ Prentice Hall 2001. Any one of the codes listed in the table 7.4, Chapter 7, section 4.6 (Best Known Convolutional Codes), page 419, in B. Sklar can be used. B. Sklar gives some FEC examples: BCH, Reed-Solomon, Convolutional codes, LDPC (Low Density Parity Check Code) ...etc. All these codes can be used as Forward Error Correction.

The block 103 is the bipolar modulation where the bits are converted into positive or negative integers (+1 and -1). The bit “0” is coded with “+1” and the bit “1” is coded with “-1”.

The encoder 120 shows an encoder according to an embodiment. The bloc 104 applies an encoding that generate a bitstream which is DC free and including parity bits.

The encoder 130 shows an encoder according to an embodiment using the ASK (Amplitude Shift Keying) modulation (106). In this case, two ECC line coders are used (105), the first for the MSB and the second for the LSB. The two ECC line coders can have different coding rates. A demultiplexer (107) is used to divide the bitstream into two bitstreams (MSB and LSB bitstreams).

Figure 2 represents an example of a convolutional code according to an embodiment. The figure 201 represents the shift register convolutional code encoder using the generator polynomials 7 (111 in binary) and 5 (101 in binary), i.e using the [7, 5] convolution code. This means that the first parity bit (CO) is computed by applying the XOR operator on the bits [S2 S1 SO] where SO is the first bit of the uncoded bitstream, inputted in the shift register. The second parity bit (C1) is computed by applying the XOR operator on the bits [S2 SO],

After each computation, the bits are shifted at right and the bits CO C1 are concatenated to form the coded bitstream.

The trellis 202 represents the [7 5] convolutional code. The continuous arrows mean that input bit equal to “0” (i.e. S2 = 0) and dashed arrows mean that the input bit is equal to “1” (i.e. S2 = 1). The trellis corresponds to the all possible transitions of the encoder, it means for each state of the encoder (S1 SO values) and for each input bit (S2 value) one can have the output bits (encoded bits C0C1).

The trellis is useful in understanding the decoding step. Indeed, the well-known Viterbi algorithm is commonly used to decode convolutional codes and this by performing two steps. The first step is the branch metric computation (BM). The Matlab"^™ code below shows how one compute the BM values for each transition starting from the received sequence noticed “r”: % Compute the Branch Metric for a received sequence 'r' BMOO = (r (2*t-D-(0) )''2+(r (2*t)-(0) )''2; BMOl = (r (2*t-D-(0) )''2+(r (2*t)-(1) )''2; BMIO = (r (2*t-D-(1) ) "-2+(r (2*t)-(0) )''2; BMll = (r (2*t-D-(1) )''2+(r (2*t)-(1) ) ^^2;

After calculating the BM values, one should compute the cumulative branch metric (CBM) of each path in the trellis by summing the branch metric of each transition that construct the said path. The Matlab'^™ code below illustrates how the CBM is calculated: % Compute the smallest Cumulative Branch Metric CBM(l,t+l) = min(CBM(l,t)+BM00,CBM(2,t)+BMll); CBM(2,t+l) = min(CBM(3,t)+BM10,CBM(4,t)+BM01); CBM(3,t+l) = min(CBM(l,t)+BMll,CBM(2,t)+BM00); CBM(4,t+l) = min(CBM(3,t)+BM01,CBM(4,t)+BM10);

Once the CBM values are computed for each path of the trellis, the path having the smallest CBM value is selected and presented at the output of the decoder. More details can be found in B Sklar.

Figure 3 represents an example of the algorithm used to generate DC free encoded bitstream from the convolutional code. A criterion used to guarantee a balance between ones and zeros is the minimization of the running digital sum (RDS).

The input bitstream of the algorithm 300 is the bitstream encoded with a convolutional code. Some bits are then modified in order to minimize the RDS value. After, the initialization of the RDS value in 302, the bloc 303 selects a bloc of A7bits so that each special bit bi belongs to one block of Ki bits and each block of Ki bits contains only the special bit bi. A special bit is a bit that is potentially inverted in order to guarantee the DC balance.

The bloc 304 computes the digital sum for two cases. The first case is when replacing the special bit bi with the bit "1" (noticed dsl) and the second case is when replacing the bit "bi" with the bit "0" (noticed dsO). The digital sum is equal to the number of ones minus the number of zeros.

The bloc 305 evaluates the condition abs(RDS+dsO) < abs(RDS+dsl).

Indeed, this will guarantee that the bit bimW be replaced by the bit value minimizing the RDS (see blocs 306 and 307).

The bloc 308 selects the next Ki block and perform the computation of dsO and dsl again (bloc 304).

Example:

Let's assume that one presents at the input of the convolutional code described in 200 the following bit sequence to be encoded: 10 10 0 1. The following encoded bit sequence will be obtained at the output of the convolutional code encoder: 1 1 1 0 0 0 1 0 1 1 1 1.

If the [1 1 1 0 1 0] puncturing code is used then the punctured codeword will be: c = [cl c2 c3 c4 c5 c6 c7 c8 c9 clO cll cl2] = [1 11x1x10x1 x]

The bits c4, c6 clO and cl2 will be appropriately chosen in order to minimize the RDS value of the whole sequence.

Preferably, the following steps are performed by the algorithm 300:

Step 1:

The RDS value is initialized to zeros

Step 2:

Start the re-encoding of the codeword c from the bit c2. To have one special bit for each three bits

Kbl = [1 1 x] (it means that: Kb2 = [1 x 1], Kb3 = [0 x 1], ...etc)

Step 3:

For Kbl compute dsl and dsO dsl for 1 1 1 = 3 ds2 for 1 1 Ο = 1

Step 4:

Compute RDS+dsO and RDS+dsl RDS +dsl = 0 + 3 = 3 RDS + dsO = 0 + 1 = 1 It means that x in Kbl is set to 0 Kbl = [1 1 0] RDS = 1

Step 5:

Select Kb2 and perform steps 2, 3 and 4.

The algorithm described in the figure 3 can be applied to generate also a Nyquist-free encoded bitstream rather than a DC-free encoded bitstream. Indeed, a parameter called AS (Alternate Sum) can be used instead of the DS (Digital Sum). The example below shows how one can compute the Alternate Sum for a bitstream.

Example:

Let’s consider the binary sequence “1100”, the AS (Alternate Sum) computation gives: AS = -1 + 1 + 1-1=0

From the AS of each sequence, one can compute the RAS (Running Alternate Sum) by a cumulative sum. In this case, the step 4 of the algorithm above will use the following equations to determine the value of the bit to be modified : RAS + ASO and RAS +AS1.

In Figure 4, Graph 401 illustrates the spectrum of an example of the encoded bitstream. One can see that the spectrum has a null power at the null frequency.

Graph 402 represents the RDS value of an example of a bitstream encoded just with the convolutional code without any DC control mechanism. One can see that the RDS value is not bounded and hence the bitstream is not DC free.

Graph 403 represents the running digital sum value computed after each K block. One can see that the RDS value of the encoded bitstream is bounded and is close to zero.

Figure 5 is flowchart of an exemplary algorithm 500 for the adaptive encoding performed according the SNR level. Indeed, the bloc 502 estimates the SNR of the channel between the transmitter and the receiver. If the SNR value is higher than a certain SNR threshold then a DC free re-encoding having a DC control based on K2 special bits among N2 encoded bits is performed. Else, a DC free re-encoding having a DC control based on K1 special bits among N1 encoded bits is performed. K2, N2, K1 and N1 are predefined such that K2/N2 is greater than Kl/Nl.

Example K2 = 1 and N2 = 3 (1 special bit among 3 bits)

Uncoded word 10 10 0 1

Codeword 111000101111

Puncturing Code 111010111010

Punctured Codeword IIIXOXIOIXIX K2 = 1 and N2 = 6 (1 sp&:ial bit among 6 bits)

Uncoded word 10 10 0 1

Codeword 111000101111

Puncturing Code 111011111011

Punctured Coeword 111X00101X11

The encoding described in 300 is applied for both cases (Kl, Nl) and (K2, N2).

In Figure 5bis, there is illustrated an exemplary algorithm 500b for the adaptive encoding performed according the current RDS value. If the absolute value of the current RDS is higher than a certain threshold then a DC free re-encoding having a DC control based on K2 special bits among N2 encoded bits is performed. Else, a DC free re-encoding having a DC control based on Kl special bits among Nl encoded bits is performed. K2, N2, Kl and Nl are predefined such that K2/N2 is greater than Kl/Nl. Figure 6 represents an exemplary simulation result in a graph 600 showing the BER comparison for (K1,N1)=(1,6) and (K2,N2)=(1,3). The BER in the figure 6 is computed with an Additive White Gaussian Noise (AWGN) -i- DC Cutoff channel.

One can see that, for high SNR, the bit error rate when using K2=l and N2=3 (i.e. 2 control bits for each 6 bits) provides a good BER in comparison to that obtained when the DC control is performed with Kl=l and Nl=6. Inversely, for low SNR, the BER for K2=l and N2=3 is higher than the BER for Kl=l and Nl=6.

One can notice that: - The error correction capacity is high for Kl=l and Nl=6 but the DC free performance (i.e. the signal power level close the null frequency) is low. - The error correction capacity is low for K2=l and N2=3 but the DC free performance (i.e. the signal power level close the null frequency) is high.

The points above explain the fact that for high SNR the number of errors obtained from the AWGN are lower than the number of errors obtained due to the DC cutoff. In this case, a DC free error correction line code having better performance in term of DC cutoff is preferred hence using K2=l and N2=3 is appropriate.

For lower SNR, the number of errors obtained due to the high level of noise are greater than the number of errors obtained due to the DC cut-off. In this case, a code having a better correction capacity is preferred (a code with Kl=l and Nl=6).

For high SNR, the number of errors obtained due to the low level of noise are lower than the number of errors obtained due to the DC cut-off. In this case, a code having a better correction capacity is preferred (a code with K2=2 and N2=6).

Figure 7 is a flowchart of steps of an algorithm 700(a) for performing the decoding. Two steps are performed in this decoding method. The first one, step 702, is to replace all the special bits (the special bits are the bits that were possibly inverted in order to guarantee a DC free property of the encoded bitstream) by an "undecided value"; not one and not zero ("0.5"). If the bitstream is modulated, the bit "1" is encoded by "+1" and the bit "0" is encoded by "-1" then the "undecided value" is equal to "0".

In the step 703, the classical Viterbi algorithm is applied as explained in the figure 2.

The algorithm 700(b) is the optimal method to perform the decoding and uses the algorithm described in the figure 9.

First, a branch metric computation for the decoding algorithm 700(b) is described with reference to Figure 8.

The trellis 802 corresponds to the example of the encoder illustrated in encoder 801. This trellis changes when the encoder 300 is used. Trellis 803 shows changes when the DC control is performed. One can see that the branch "00" of the arrow linking the two states "00" and "00" can take the value "01" depending on the RDS value of the state 00 and the position of the special bit. The RDS of the state 00 corresponds to the running digital sum of the survival path arriving to the state 00. If the value of the RDSOO is negative and Y is considered as a special bit according to the used puncturing code then the Y bit is selected to be 1. The branch metric is computed with a XY = 01 in this case. This means that the trellis weights (00, 01, 10, 11) varies according to the running digital sum of the survival paths and the position of the special bits (puncturing code).

An example of computation of the branch metric is illustrated in 804. The classical Euclidean distance may be used.

The algorithm starts with the initialization of the cumulative branch metric (CMB(s,0)) and the running digital sum (RDS(s,0)) of each state of the trellis at the step 0 (block 902).

The branch metric of the transition from the step 0 to the step one is computed according to the RDS(s,0), the presence or not of the special bit in the transition state zero to state one; and the received sequence to be decoded (block 903). This is done for each state of the trellis.

The block 904 updates the current cumulative branch metric (CBM(s,l)) according to the computed branch metric obtained from 903 and the previous cumulative branch metric values. This is done for each state of the trellis. The classical Viterbi algorithm is used here to update the CBM values by selecting the each branch that minimize each survival path. This step is performed for a given number of steps.

The block 905 selects one survival path among the survival paths associated to each state of the trellis. The selected path has the lowest cumulative branch metric.

The block 906 performs the classical traceback in order to determine the encoded sequence (this traceback function is the same as used in the Viterbi algorithm).

Figure 10 is a schematic block diagram of a general architecture of a device 1000 for implementing of one or more embodiments of the invention. The device 1000 comprises a communication bus connected to: - a central processing unit (or control unit) 1001, such as a microprocessor, denoted CPU; - a random access memory 1002, denoted RAM, for storing the executable code of the method of embodiments of the invention as well as the registers adapted to record variables and parameters necessary for implementing a method according to embodiments, the memory capacity thereof can be expanded by an optional RAM connected to an expansion port for example; - a read only memory 1003, denoted ROM, for storing computer programs for implementing embodiments of the invention; - a network interface 1004 is typically connected to a communication network over which digital data to be processed are transmitted or received. The network interface 1004 can be a single network interface, or composed of a set of different network interfaces (for instance wired and wireless interfaces, or different kinds of wired or wireless interfaces). Data are written to the network interface for transmission or are read from the network interface for reception under the control of the software application running in the CPU 1001; - a user interface 1005 for receiving inputs from a user or to display information to a user;

- a hard disk 1006 denoted HD - an I/O module 1007 for receiving/sending data from/to external devices such as a video source or display

The executable code may be stored either in read only memory 1003, on the hard disk 1006 or on a removable digital medium such as for example a disk. According to a variant, the executable code of the programs can be received by means of a communication network, via the network interface 1004, in order to be stored in one of the storage means of the device 1000, such as the hard disk 1006, before being executed.

The central processing unit 1001 is adapted to control and direct the execution of the instructions or portions of software code of the program or programs according to embodiments of the invention, which instructions are stored in one of the aforementioned storage means. After powering on, the CPU 1001 is capable of executing instructions from main RAM memory 1002 relating to a software application after those instructions have been loaded from the program ROM 1003 or the hard-disc (HD) 1006 for example. Such a software application, when executed by the CPU 1001, causes the steps of a method according to embodiments to be performed.

Although the present invention has been described hereinabove with reference to specific embodiments, the present invention is not limited to the specific embodiments, and modifications will be apparent to a skilled person in the art which lie within the scope of the present invention.

Many further modifications and variations will suggest themselves to those versed in the art upon making reference to the foregoing illustrative embodiments, which are given by way of example only and which are not intended to limit the scope of the invention, that being determined solely by the appended claims. In particular the different features from different embodiments may be interchanged, where appropriate.

In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that different features are recited in mutually different dependent claims does not indicate that a combination of these features cannot be advantageously used.

Claims

1. A method of processing a bitstream comprising a plurality of encoded codewords, the method comprising: obtaining an encoded codeword comprising a plurality of bits, each of the plurality of bits being associated with a bit position in the codeword; obtaining a puncturing code designating bit-positions of the codeword to be punctured prior to decoding; obtaining a modified codeword by modifying at least one bit of the codeword at a bit-position designated by the puncturing code in order to keep the value of a digital sum (RDS) and/or a running alternate sum (RAS) bounded.

2. The method according to claim 1, further comprising a step of determining if modification of the codeword is needed, the said step comprising checking if the value of digital sum (RDS) and/or a running alternate sum (RAS) of the codeword is not bounded.

3. The method according to claim 1 or claim 2 further comprising a step of transmitting the modified codeword.

4. The method according to any one of claims 1, 2 or 3 wherein the puncturing code is based at least in part on a measure of channel quality.

5. The method according to claim 4 wherein the measure of channel quality is a measured signal to noise ratio.

6. The method according to claim 4 or claim 5, wherein the puncturing code is obtained independently at a transmitting device modifying the codeword and at a receiving device receiving the modified codeword.

7. The method according to any one of claims 1 to 5, wherein the puncturing code is communicated from a transmitting device modifying the codeword to a receiving device receiving the modified codeword.

8. The method according any one of claims 1 to 7, wherein the puncturing code is based at least in part on the minimum number of bits that need to be modified to reach a DC-free state and/or a Nyquist-free state.

9. The method according to any preceding claim, further comprising receiving the modified codeword at a receiving device and puncturing the received modified codeword at the at least one bit-position designated by the puncturing code.

10. The method according any one of the previous claims wherein the encoded codeword is obtained by performing an error correction coding.

11. The method according to claim 10, further comprising transmitting said encoded codeword, wherein the error correction coding is a punctured convolution coding and wherein no puncturing is performed before transmission.

12. A device for processing a bitstream comprising a plurality of encoded codewords, the device comprising a control unit configured to obtain an encoded codeword comprising a plurality of bits, each of the plurality of bits being associated with a bit position in the codeword; obtain a puncturing code designating bit-positions of the codeword to be punctured prior to decoding; and obtain a modified codeword by modifying at least one bit of the codeword at the bit-positions designated by the puncturing code in order to keep the value of a digital sum (RDS) and/or a running alternate sum (RAS) bounded.

13. The device according to claim 12, wherein said control unit is further configured to carry out a determination of whether the modification of the codeword is needed, and wherein the determination comprises checking if the value of digital sum (RDS) and/or a running alternate sum (RAS) of the codeword is not bounded.

14. The device according to claim 12 or claim 13, wherein said control unit is further configured to transmit the modified codeword.

15. The device according to any one of claims 12 to 14, wherein the puncturing code is based at least in part on a measure of channel quality.

16. The device according to claim 15, wherein the measure of channel quality is a measured signal to noise ratio.

17. The device according to claim 15 or claim 16, wherein the puncturing code is obtained independently at the device and at a receiving device to which the modified codeword is transmitted.

18. The device according to any one of claims 14 to 17, wherein the control unit is further configured to communicate the puncturing code to a receiving device to which the modified codeword is transmitted.

19. The device according to any one of claims 12 to 18, wherein the puncturing code is based at least in part on the minimum number of bits that need to be modified to reach a DC-free state and/or a Nyquist-free state.

20. The device according to any one of claims 12 to 19, wherein the encoded codeword is obtained by performing an error correction coding.

21. The device according to claim 20, wherein the control unit is further configured to transmit the encoded codeword, wherein the error correction coding is a punctured convolution coding and wherein no puncturing is performed before transmission.

22. An encoding device according to any one of claims 12 to 21, wherein said control unit if further configured to generate said encoded codewords.

23. A decoding device for decoding a bitstream comprising a plurality of encoded codewords, each encoded codeword comprising a plurality of bits, each of the plurality of bits being associated with a bit position in the codeword, wherein at least one encoded codeword is a modified codeword modified by modifying at least one bit of codeword at a bit-position designated by a puncturing code in order to keep the value of a digital sum (RDS) and/or a running alternate sum (RAS) bounded, the decoding device comprising a control unit configured to obtain said puncturing code, perform a puncturing of said at least one modified encoded codeword and decode said encoded codeword.

24. The device according to claim 23, wherein the puncturing code is obtained independently at the decoding device and at a device transmitting the modified codeword.

25. The device according to any one of claims 23 to 24, wherein the control unit is further configured to receive the puncturing code from a device performing the modification of the encoded codeword.

26. The device according to any one of claims 23 to 25, wherein the puncturing code is based at least in part on the minimum number of bits that need to be modified to reach a DC-free state and/or a Nyquist-free state.

27. A system comprising: - an encoding device according to claim 22, and - a decoding device according to claim 32 for decoding a bitstream encoded by said encoding device.

28. A computer program product comprising instructions for implementing a method according to any one of claims 1 to 11 when the program is loaded and executed by a programmable apparatus.

29. A non-transitory information storage means readable by a computer or a microprocessor storing instructions of a computer program, for implementing a method according to any one of claims 1 to 11, when the program is loaded and executed by the computer or microprocessor.

30. A device substantially as hereinbefore described with reference to, and as shown in. Figures 1 and 10 of the accompanying drawings.

31. A method substantially as hereinbefore described with reference to, and as shown in, Figures 3, 5, 5bis, 7 and 9 of the accompanying drawings.

31. A method substantially as hereinbefore described with reference to, and as shown in. Figures 3, 5, 5bis, 7 and 9 of the accompanying drawings. AMENDMENTS TO CLAIMS HAVE BEEN FILED AS FOLLOWS CLAIMS

11. The method according to claim 10, further comprising transmitting said encoded codeword, vv'herein the error correction coding is a punctured convolution coding and wherein no puncturing is performed before transmission.

16. The device according to ciaim 15, wherein the measure of channel quality is a measured signal to noise ratio.

17. The device according to ciaim 15 or ciaim 16, wherein the puncturing code is obtained independently at the device and at a receiving device to which the modified codeword is transmitted.

22. An encoding device according to any one of claims 12 to 21, wherein said control unit is further configured to generate said encoded codewords.

23. A decoding device for decoding a bitstream comprising a plurality of encoded codewords, each encoded codeword comprising a plurality of bits, each of the plurality of bits being associated with a bit position in the codeword, wherein at least one encoded codeword is a modified codeword modified by modifying at least one bit of codeword at a bit-position designated by a puncturing code in order to keep the value of a digital sum (RDS) and/or a running alternate sum (RAS) bounded, the decoding device comprising a control unit configured to obtain said puncturing code, perform a puncturing of said at least one modified encoded codew'ord and decode said encoded codeword.

25. The device according to any one of claims 23 to 24, wherein the control unit is further configured to receive the puncturing code from a device performing the modification of the encoded codeword,

27. A system comprising: - an encoding device according to claim 22, and - a decoding device according to claim 23 for decoding a bitstream encoded by said encoding device.

29. A non-transitory information storage means readable by a computer or a microprocessor storing instructions of a computer program, for implementing a method according to any one of claims 1 to 11, when the program is loaded and executed by the computer or microprocessor

30. A device substantially as hereinbefore described with reference to, and as shown in, Figures 1 and 10 of the accompanying drawings.