GB2538768A

GB2538768A - Bipolar power semiconductor transistor

Info

Publication number: GB2538768A
Application number: GB1509160.6A
Authority: GB
Inventors: Ward Peter
Original assignee: Anvil Semiconductors Ltd
Current assignee: Anvil Semiconductors Ltd
Priority date: 2015-05-28
Filing date: 2015-05-28
Publication date: 2016-11-30
Also published as: WO2016189308A1; GB201509160D0

Abstract

A bipolar power semiconductor transistor 100 or method of manufacturing the same comprises a semiconductor drift region 130 of a second conductivity type comprising 4-step hexagonal silicon carbide (4H-SiC); a first semiconductor region 110 comprising 3-step cubic silicon carbide (3C-SiC) of a first conductivity type disposed over a first surface of the semiconductor drift region; a 3C-SiC body region 140 of the first conductivity type located on or within the semiconductor drift region; the body region being adjacent to a second surface of the drift region opposite the first surface of the drift region; a source region 150 (which may be 3C-SiC) of the second conductivity type located within the body region; and a gate 180 placed above the source region, the gate controls charge in a channel region 170 between the semiconductor drift region and the source region and thereby controls flow of charge within the semiconductor drift region. The device may include a buffer region between the first semiconductor region and the semiconductor drift region.

Description

Bipolar Power Semiconductor Transistor

FIELD OF THE INVENTION

This invention relates to a power semiconductor transistor, particularly but not exclusively, to a bipolar power semiconductor transistor.

BACKGROUND TO THE INVENTION

The energy saving advantages of using silicon carbide (SiC) components in power conversion and conditioning systems are well known in the voltage range 650V to 10 kV. However, there is a demand to utilise SiC in heavy traction and high-voltage direct current (HVDC) applications which demand much higher voltages.

The switches in power conversion systems can be metal-oxide-semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs); the former have the advantage of being able to switch faster, but being majority carrier only devices the on-resistance of the off-voltage sustaining (drift) region is directly proportional to the voltage rating of the switch. Therefore over certain voltages (roughly 1 kV for Si and 10 kV for SiC) the IGBT is the preferred device. It utilises both majority and minority carriers in such a way that the drift region is conductivity modulated in the on-state and consequently the on-resistance is substantially reduced. The price paid for this advantage is a reduced switching speed due to the need to remove the minority carriers during switch-off.

Given these considerations then the device of choice for high efficiency switches above 10kV is SiC IGBTs, in other words a normal n-channel MOSFET with a p-type injector added to a drain structure. However there are considerable barriers to producing such a device. The commonest polytype of SiC is the 4-step hexagonal version (4H-SiC), but this material is difficult to process because ion implantation damage is not readily repaired and it is not reactive enough with normal metals to make metallisafion simple. Further the MOSFETs produced on 4H-SiC have poor carrier mobility under the MOSFET gate adding substantially to the on-resistance to the transistor. This latter point is less important as the drift region thickness is increased to produce higher voltage MOSFET devices, but becomes very important in the IGBT context where the drift region resistance is minimised by minority carrier conductivity modulation. It is therefore apparent that the channel resistance in a 4H-SiC IGBT would be significantly higher to increase the overall on-state resistance of the IGBT.

One of the many alternative SiC polytypes is the 3-step cubic form (30-SiC), it has been demonstrated that this polytype does not suffer from the problems noted above, but it cannot be produced as a stand-alone crystal and must be grown epitaxially on a substrate, for example silicon or 4H-SiC (see CVD growth of 3C-S1C on 4H-SiC substrate. Anne Henry et aL 2012, Material Science Forum, 711, 16-21). When grown on Silicon there are considerable tensile stress problems to overcome and normally the additional cost of utilizing 3C-SiC grown on 4H-SiC for a MOSFET cannot be justified.

"N-Channel 3C-SIC MOSFETs on Silicon Substrate; Jianwei Wan et at IEEE Electron Device Letters, Vol. 23, No. 8, August 2002" describe 3C-S1C MOSFETs having very high carrier mobility.

"Electrical Properties and Interface Chemistry in the Ti/3C-SiC System; Fetid Touati et a/; IEEE Transactions On Electron Devices, Vol. 46, No. 3, March 1999" describe that low temperature silicides can be used as metallisafion layers in 3C-SiC processing steps.

It is an object of the present invention to address the problems discussed above.

SUMMARY

According to one aspect of the present invention, there is provided a bipolar power semiconductor transistor comprising: a semiconductor substrate of a second conductivity type, the semiconductor substrate forms a semiconductor drift region; a first semiconductor region of a first conductivity type, opposite the second conductivity type, disposed over a first surface of the semiconductor drift region; a body region of the first conductivity type located on or within the semiconductor drift region; the body region being adjacent to a second surface of the drift region, the second surface of the drift region being opposite the first surface of the drift region; a source region of the second conductivity type located within the body region; a gate placed above the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; wherein the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC); wherein the semiconductor drift region comprises a material comprising 4-step hexagonal silicon carbide (4H-SiC), and wherein the body region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).

To produce an n-channel IGBT a thick n-drift region is required, typically in higher voltage silicon devices this drift region is formed by a whole n-float zone (FZ) wafer, and then the device structures are added to the front and back sides. This may not be straightforward in SiC technology since normal Physical Vapour Transport (PVT) crystal growth results in an n+ wafer because of the ubiquity of the n-type SiC dopant Nitrogen. However, a High Temperature Chemical Vapour Deposition (HTCVD) crystal growth technique has been developed which is capable of producing the lightly doped material needed for this application. The HTCVD technique is described in US2005/0000406, which is incorporated herein by reference. The critical electric field for 4H-SiC is about 200V per pm which is possible to achieve using the HTCVD technique. A 100 pm thick wafer can generally be sufficient for a 20 kV device and for such a rating the HTCVD technique can manufacture the 100 pm drift region. Higher voltage devices require thicker base wafers which are in fact easier to manufacture using 4H-SiC.

In summary the proposed technique includes growing 3C-SiC on the front and back sides of an HTCVD 4H-SiC wafer or drift region to facilitate the formation of a high quality MOSFET On the front side) and p-injector region (in the back side). Thus the overall device forms a vertical IGBT which has very high carrier mobility in the channel region due to the use of the 3C-SiC material. Thus the IGBT has a much lower channel resistance compared to an IGBT in which 4H-SiC is used in the channel region. Furthermore, the 4H-SiC drift region can be at least about 100 pm (and possibly more) so that a breakdown voltage of about 20KV can be sustained by the IGBT. The fundamental advantage of this approach is to produce the highest quality, lowest on-resistance device, together with the easier processing of 3C-SiC. The 3C-SiC process utilizes easier equipment and low temperature (about 1350°C) silicon oxide (Si02). By contrast, the 4H-SiC process works in a very high temperature in which an implantation is annealed at about 1600°C to 1800°C.

Further, the addition of the 3C-SiC p-injector (or the first semiconductor region) allows the injector structure to be grown epitaxially resulting in a simple low-cost process. The presence of 3C-SiC on the back of the wafer will also facilitate the back metallisation since low temperature silicides can be used.

The source region may comprise a material comprising 3-step cubic silicon carbide (3C-SiC). The source region can also be referred to an emitter region in the IGBT structure.

The gate may be configured to form an n-channel between the source region and the semiconductor drift region through which electron can be injected to the semiconductor drift region.

The n-channel may comprise a material comprising 3-step cubic silicon carbide (3C-SiC). The channel is mainly formed within the body region The transistor may further comprise a second semiconductor region between the first semiconductor region and the drift region. The second semiconductor region may comprise a material comprising 4H-SiC. The second semiconductor region is highly doped. The Since the drift region is lowly doped and made with 4H-SiC, the highly doped second semiconductor region may provide an interface layer made with 4H-SiC between the highly doped first (injector) region and the lowly doped drift region.

The transistor may be an insulated gate bipolar transistor (IGBT). The transistor may be a vertical IGBT. The transistor may be a non-punch through insulated gate bipolar transistor (NPT-IGBT).

The transistor may further comprise a buffer region of the first conductivity type between the first semiconductor region and the semiconductor drift region, the buffer region having lower doping concentration than the first semiconductor region. The transistor may be a punch-through insulated gate bipolar transistor (PT-IGBT). The buffer region may comprise a material having 4-step hexagonal silicon carbide (4HSiC). The buffer region may have a length of about 5 pm. The doping concentration of the buffer region may be about 5e17cm-3.

The length of the body region may be up to about 5 pm. The body region has a p-type doping concentration of about 2e15cm-3. The p-type doping may be implanted on an n3C-SiC epitaxial layer.

The length of the drift region may be about 100 pm. The drift region may be double-side polished. The length of the drift region may be such that the transistor is configured to operate at over 10KV, preferably at about 20kV.

The length of the first semiconductor region or the injector structure may be up to about 2 pm. The doping concentration of the first semiconductor region may be about 1e19 CM-3.

The first semiconductor region may be an injection region configured to inject charge into the semiconductor drift region.

The transistor may further comprise an ohmic contact layer being operatively connected to the injector region. The ohmic contact layer may comprise a material comprising Titanium Silicide (TiSi2).

The transistor may further comprise an ohmic contact layer being operatively connected to the source region. The ohmic contact layer may comprise a material comprising Titanium Silicide (TiSi2). The same TiSi2 layer may be connected to poly silicon material of the gate. The gate may thus be formed with Titanium Silicone material (formed from the combination of TiSi2 and poly silicon). Thus a self-aligned device structure can be made. This also allows producing a relatively compact and cost-effective device. TiSi2 is not possible to use in 4H-SiC process because TiSi2 would not survive in the relatively high temperature (-1000°C) of the 4H-SiC processing.

The drift region may be configured to be depleted of mobile carriers at a breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor.

According to a further aspect of the present invention, there is provided a method of manufacturing a bipolar power semiconductor transistor, the method comprising: forming a semiconductor substrate which forms a drift region using a material comprising 4-step hexagonal silicon carbide (4H-SiC); forming a first semiconductor region over a first surface of the semiconductor drift region, the first semiconductor region being formed using 3-step cubic silicon carbide (3C-SiC) material; forming a body region on a second surface of the semiconductor drift region, the body region being formed using 3-step cubic silicon carbide (3C-SiC) material; forming a source region within the body region; and forming a gate above the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow to charge, within the semiconductor drift region.

The source region may comprise a material comprising 3C-SiC.

Preferably the semiconductor substrate, the first semiconductor region and the body region are each of a first conductivity type, and the semiconductor drift region and the source region are each of a second conductivity type opposite to the first conductivity type.

The semiconductor drift region may be formed using a High Temperature Chemical Vapour Deposition (HTCVD) crystal growth technique.

Prior to forming the first semiconductor region and the body region, the drift region is cut and polished in both sides of the drift region.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only.

Figure 1 illustrates a schematic cross section of an IGBT; Figure 2 illustrates an equivalent circuit diagram of the IGBT of Figure 1; Figure 3 illustrates a schematic cross section of an alternative IGBT, and Figure 4 illustrates a schematic cross section of an alternative IGBT.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to Figure 1, an example of a vertical power semiconductor transistor 100 in the form of an insulated gate bipolar transistor (IGBT) is shown. The transistor 100 has first and second semiconductor layers 110, 130 (or a first semiconductor region and a drift region) formed using silicon carbide (SiC) materials. The first semiconductor layer 110 includes 3C-SiC material and the second semiconductor layer (or the drift region) includes 4H-SiC material. The first semiconductor layer 110 provides a p-type collector which is formed over a first surface of the drift region 130. P-type wells at a second surface 160 (which is opposite the first surface) of the drift layer 130 provide body regions 140. N-type wells within the p-type body regions 140 provide contact regions and provide sources/emitters 150. The body region 140 and the source region can be formed using 3C-SiC material. A channel 170 is formed beneath a gate 180 which is separated using a gate dielectric (oxide) layer 190. The channel 170 formed within the body region 140 comprises 30-SiC material.

The IGBT shown in Figure 1 is able to support much greater breakdown voltages (from about 10KV to about 20KV) due to the use of 4H-SiC in the drift region 130, which can be extended at least about 100 pm The length of the drift layer can be more than 100 pm to achieve a higher breakdown voltage. Since it is possible to form a much longer drift region using 4H-SiC, the IGBT is capable of operating in much higher breakdown voltages (from about 10KV to about 20KV). At the same time the on-resistance of the IGBT can be significantly improved. This is because a better channel mobility is observed in the 3C-SiC channel region 170 (compared to 4H-SiC), and therefore the on-resistance of the 30-SiC channel region formed between the drift region 130 and the source/emitter region 150 can be significantly reduced.

It will be appreciated that a heterostructure is formed between the drift region 130 (having 4H-SiC) and p+ 3C-SiC layer 120. The 3C-SiC material in the first semiconductor layer 110 (-2 pm) just above the SIC/Si interface 200 is very heavily defective because of the lattice miss-match between the two materials and heavily doped with aluminium (Al) as-grown, consequently this defective region can be very conductive.

The process sequence for fabricating the IGBT of Figure 1 is described below: 1. Cut and polish both sides of a 4H-SiC wafer which becomes the drift region 130 2. Grow injector structure on a Carbon face or a first surface of the 4H-SiC wafer.

The injector structure is the first semiconductor region 110 The injector structure includes 3C-SiC.

3. Thermally oxidise wafer to protect back, dip off oxide on the silicon face.

4. Grow front device epitaxial layer on the silicon face or a second surface of the 4H-SiC wafer. The device epitaxial layer used to form the MOSFET structure including a short n-drift region.

5. Perform a MOSFET processing at the Si face (the second surface). It would be appreciated that the MOSFET processing forms a MOSFET structure comprising the source region 150, the body region 140 and the drift region 130.

When the injector structure or the first semiconductor layer 120 is incorporated then the device becomes an IGBT.

6. Form metallisafion on front and back faces/surfaces simultaneously.

Since the source/emitter 150 and the collector (the first semiconductor region) 110 are highly doped, it is possible to form ohmic contacts operatively connected to these regions. In one embodiment, the ohmic contacts are formed using TiSi2 material. This material is generally usable in 3C-SiC processing steps which require much lower temperature (compared to the temperature used in a 4H-SiC process). The ohmic contact 180 connecting the source region 150 can also be extended over the body 140 and drift region 130 to form part of the gate. Thus it is possible to form a self-aligned structure using the 3C-S1C process.

The on-state and off-state operations of the IGBT 100 are described below.

The IGBT as shown in Figure 1 has within its structure two MOS-bipolar devices: (i) A cascade MOSFET-PIN diode; 00 A MOS base current controlled -wide base PNP transistor.

The equivalent circuits for these components of the IGBT structure 100 are shown in Figure 2.

In the off-state a reverse biased PIN diode (formed by the first region 110, drift region 130 and body region 140) serves to support the high voltage applied between the emitter 150 and collector 120.

The transistor 100 can be turned-on by applying a positive voltage to the gate 180 with respect to the emitter 150 to invert the p base surface under the insulated gate 180.

The channel 170 is then formed at the surface of the body region 140, between the n+ emitter 150 and the n-drift region 130, which allows electrons to be injected into the n-drift region 130. This electron current serves as a base current for the bipolar PNP transistor formed between the p+ emitter 150, the n-drift region (base) 130 and the p+ 3C-SiC collector 110. Once the PNP transistor (within the IGBT 100) is turned on, excess carrier charge (plasma) builds up in the lowly-doped n-drift region 130 and the conductivity of this layer increases significantly.

The transistor 100 can be turned-off by short-circuiting the gate voltage to the emitter 150 which cuts off the supply of electrons to the base (the drift region 130) of the PNP transistor within the IGBT 100 as described above. The turn-off speed of the device is determined by the open base current decay of the PNP transistor within the IGBT 100 which in turn is dependent on the excess carrier charge (plasma) stored in the n-drift region 130.

Figure 3 illustrates a schematic cross section of an alternative IGBT. Many features of the IGBT of Figure 3 are the same as the feature of the IGBT of Figure 1, except that the IGBT of Figure 3 includes a second semiconductor region 120 between the first semiconductor (injector) region 110 and the drift region 120. The second semiconductor region is of p-type and highly doped. The second semiconductor region 120 includes 4H-SiC material. Since the drift region 130 is lowly doped and made with 4H-SiC, the highly doped second semiconductor region 120 provides an interface layer made with 4H-SiC between the highly doped first (injector) region 110 and the lowly doped drift region 130. It would be appreciated that the second semiconductor region 120 may not be essential for the operation of the transistor. Further, the second semiconductor region 120 may be formed with n-type material as well.

The IGBT 100 of Figures 1 and 3 is a non-punch through (NPT) IGBT in which the n-drift region 130 has a longer length such that, during the off-state, the depletion region in the drift region 130 does not reach the p+ SIC layer 120.

Figure 4 illustrates a schematic cross-section of a punch-through (PT) IGBT 300. Many features of the IGBT in Figure 4 are the same as those shown in Figure 3 and therefore carry the same reference numerals. However, the IGBT structure 300 in Figure 4 has an additional layer which is a buffer layer 310 between the p+ SiC layer (second semiconductor region) 120 and the n-drift region 130. The buffer layer 310 is an n type layer having higher doping concentration than the n-drift region 130. The buffer layer 310 includes 4H-SiC. The n buffer 310 can have a double role: it stops the depletion region to reach the collector 120 and it adjust the injection efficiency of the collector junction. This helps to control the plasma growth during on-state and thus control the trade-off between the on-state losses and turn-off speed and losses.

It will be appreciated that the doping concentrations of various layers of the transistors discussed with reference to Figures 1 to 4 are those used in the corresponding state of the art transistors.

The skilled person will understand that in the preceding description and appended claims, positional terms such as 'above', 'overlap', 'under', 'lateral', vertical', etc. are made with reference to conceptual illustrations of a transistor, such as those showing standard cross-sectional perspectives and those shown in the appended drawings.

These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a transistor when in an orientation as shown in the accompanying drawings.

It will be noted that the term "first conductivity type" can refer to a p-type doping polarity and the term "second conductivity" can refer to a n-type doping polarity. However, these terms are not restrictive. It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention. It will be appreciated that the emitter, collector and gate could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present invention.

Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS: 1. A bipolar power semiconductor transistor comprising: a semiconductor substrate of a second conductivity type, the semiconductor substrate forms a semiconductor drift region; a first semiconductor region of a first conductivity type, opposite the second conductivity type, disposed over a first surface of the semiconductor drift region; a body region of the first conductivity type located on or within the semiconductor drift region; the body region being adjacent to a second surface of the drift region, the second surface of the drift region being opposite the first surface of the drift region; a source region of the second conductivity type located within the body region; a gate placed above the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow of charge within the semiconductor drift region; wherein the first semiconductor region comprises a material comprising 3-step cubic silicon carbide (3C-SiC); wherein the semiconductor drift region comprises a material comprising 4-step hexagonal silicon carbide (4H-SiC), and wherein the body region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
2. A transistor according to claim 1, wherein the source region comprises a material comprising 3-step cubic silicon carbide (30-SiC).
3. A transistor according to any preceding claim, wherein the gate is configured to form an n-channel between the source region and the semiconductor drift region through which electron can be injected to the semiconductor drift region.
4. A transistor according to claim 3, wherein the n-channel formed within the body region comprises a material comprising 3-step cubic silicon carbide (3C-SiC).
5. A transistor according to claim any preceding claim, further comprising a second semiconductor region between the first semiconductor region and the drift region.
6. A transistor according to claim 5, wherein the second semiconductor region comprises a material comprising 4H-SiC.
7. A transistor according to any preceding claim being an insulated gate bipolar transistor (IGBT).
8. A transistor according to any preceding claim being a non-punch through insulated gate bipolar transistor (NPT-IGBT).
9. A transistor according to any one of claims 1 to 7, further comprising a buffer region of the first conductivity type between the first semiconductor region and the semiconductor drift region, the buffer region having lower doping concentration than the first semiconductor region.
10. A transistor according to claim 9 being a punch-through insulated gate bipolar transistor (PT-IGBT).
11. A transistor according to claim 9 or 10, wherein the buffer region comprises a material having 4H-SiC.
12. A transistor according to any preceding claim, wherein the length of the body region is up to about 5 pm.
13. A transistor according to any preceding claim, wherein the length of the drift region is at least about 100 pm.
14. A transistor according to any preceding claim, wherein the length of the drift region is such that the transistor is configured to operate at about 20kV.
15. A transistor according to any preceding claim, wherein the length of the first semiconductor region is up to about 2 pm.
16. A transistor according to any preceding claim, wherein the first semiconductor region is an injection region configured to inject charge into the semiconductor drift region.
17. A transistor according to claim 16, further comprising an ohmic contact layer being operatively connected to the injector region, wherein the ohmic contact layer comprises a material comprising Titanium Silicide (TiSi2).
18. A transistor according to any preceding claim, further comprising an ohmic contact layer being operatively connected to the source region, wherein the ohmic contact layer comprises a material comprising Titanium Silicide (TiSi2).
19. A transistor according to claim 18, wherein the same TiSi2 layer forms the material of the gate.
20. A transistor according to any preceding claim, wherein the drift region is configured to be depleted of mobile carriers at a breakdown voltage during an off-state blocking mode of the transistor and able to conduct charge during an on-state conducting mode of the transistor.
21. A method of manufacturing a bipolar power semiconductor transistor, the method comprising: forming a semiconductor substrate which forms a drift region using a material comprising 4-step hexagonal silicon carbide (4H-SiC); forming a first semiconductor region over a first surface of the semiconductor drift region, the first semiconductor region being formed using 3-step cubic silicon carbide (3C-SiC) material; forming a body region on a second surface of the semiconductor drift region, the body region being formed using 3-step cubic silicon carbide (3C-SiC) material; forming a source region within the body region; and forming a gate above the source region, the gate to control charge in a channel region between the semiconductor drift region and the source region and to thereby control flow to charge, within the semiconductor drift region.
22. A method according to claim 21, wherein the source region comprises a material comprising 3C-SiC.
23. A method according to claim 21 or 22, wherein the first semiconductor region and the body region are each of a first conductivity type, and wherein the drift region and the source region are each of a second conductivity type opposite to the first conductivity type.
24. A method according to any one of claims 21 to 23, wherein the semiconductor drift region is formed using a High Temperature Chemical Vapour Deposition (HTCVD) crystal growth technique.
25. A method according to any one of claims 21 to 24, wherein prior to forming the first semiconductor region and the body region, the drift region is cut and polished in both sides of the drift region.
26. A bipolar power semiconductor transistor, and a method for manufacturing the semiconductor transistor, substantially as hereinbefore described with reference to and as illustrated, in the accompanying drawings.