GB2534544A - Hybrid device - Google Patents

Hybrid device Download PDF

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Publication number
GB2534544A
GB2534544A GB1422127.9A GB201422127A GB2534544A GB 2534544 A GB2534544 A GB 2534544A GB 201422127 A GB201422127 A GB 201422127A GB 2534544 A GB2534544 A GB 2534544A
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United Kingdom
Prior art keywords
region
jfet
hemt
hybrid device
conduction
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GB1422127.9A
Inventor
Bryant Angus
Andrew Mawby Philip
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WARWICK VENTURES
Maschinenfabrik Reinhausen GmbH
Original Assignee
Maschinenfabrik Reinhausen GmbH
Maschinenfabrik Reinhausen Gebrueder Scheubeck GmbH and Co KG
WARWICK VENTURES Ltd
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Application filed by Maschinenfabrik Reinhausen GmbH, Maschinenfabrik Reinhausen Gebrueder Scheubeck GmbH and Co KG, WARWICK VENTURES Ltd filed Critical Maschinenfabrik Reinhausen GmbH
Priority to GB1422127.9A priority Critical patent/GB2534544A/en
Priority to PCT/EP2015/079297 priority patent/WO2016092031A1/en
Priority to TW104141659A priority patent/TW201633534A/en
Publication of GB2534544A publication Critical patent/GB2534544A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
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    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A hybrid device combines a Junction Field Effect Transistor (JFET) and High Electron Mobility Transistor (HEMT) device structure. The hybrid device has a drain terminal, a source terminal and a gate terminal and comprises: a HEMT; and a JFET coupled in series with the HEMT, wherein each of the HEMT and the JFET comprises a gate region, a source conduction region and a drain conduction region, and wherein the gate region of the JFET is coupled to a first said conduction region of the HEMT.

Description

HYBRID DEVICE
FIELD OF THE INVENTION
This invention generally relates to a hybrid device such as a hybrid power semiconductor device, a combined JFET and HEMT device structure, and a method of fabricating a combined JFET and HEMT device structure.
BACKGROUND TO THE INVENTION
Considering conventional HEMTs (High Electron Mobility Transistor), JFETs (Junction Field Effect Transistor) and MOSFETs (metal oxide field effect transistor), the attributes of each device type are, broadly speaking, as follows (* indicates a disadvantage): Attribute GaN SiC Device type HEMT JFET MOSFET Device construction *Lateral Vertical Vertical Device mode Normally-off *Normally-on Normally-off Substrate Si N+ SiC N+ SiC Channel mobility High --- *Low Bipolar devices have been constructed in SiC but still suffer from forward voltage drop (conduction losses) increasing throughout the lifetime due to growth of basal plane dislocations during operation.
Regarding GaN HEMTs, these have made good progress in recent years, with some devices grown on Si substrates (although SiC is a preferred substrate because of the good lattice match between GaN and SiC). The conduction losses are very low due to the high mobility electron gas in the HEMT structure. However, achieving reliable devices with breakdown voltages above 200 V is challenging, due to current collapse. Furthermore, the absence of a readily available GaN substrate limits the device to using a lateral structure, which makes high voltage devices occupy relatively large areas and limits the practical breakdown voltage..
Regarding SiC JFETs, these have been commercially available for some years, and have low conduction losses. However, the normally-on mode of operation inherent to JFETs limits their potential; some devices are used in cascode-like operation with Si MOSFETs to overcome this drawback.
Regarding SiC MOSFETs, these devices are advantageous for use in power converters, since they are normally-off switches and are vertical devices, so have good utilisation of device area. However, they have suffered greatly from poor MOS channel conduction (low mobility) due to the levels of defects at the interface between the gate oxide (SiO2) and the SiC P-well. The channel resistance is generally a limiting factor in devices with breakdown voltages below 1200 V where the channel resistance is large compared with the drift region resistance.
There therefore remains a need for a device having advantage such as, inter alia, operable at high temperature, high voltage (e.g., voltage rating within the 600 -900V range) and/or high frequency, and/or that is more reliable for example by virtue of a higher breakdown voltage, is normally off and/or consumes less power in operation for example due to good channel conduction, etc.
SUMMARY
According to a first aspect of the present invention, there is provided a hybrid device having a drain terminal, a source terminal and a gate terminal, wherein the hybrid device comprises: a HEMT; and a JFET coupled in series with the HEMT, wherein each of the HEMT and the JFET comprises a gate region, a source conduction region and a drain conduction region, and wherein the gate region of the JFET is coupled to a first said conduction region of the HEMT.
Preferably (i.e., optionally), the hybrid device is a hybrid power semiconductor device. The HEMT may be a normally-off HEMT, e.g., an enhancement mode HEMT.
Such a device may in embodiments allow a normally-off device. The device may for example provide an improvement or alternative to a conventional HEMT, JFET or MOSFET. The device may have a voltage rating within 600V -900V, and may thus be suitable for, e.g., automotive traction and/or domestic solar inverters. For example, the device(s) may be used as power switches for a power converter, e.g., ac-ac, ac-dc, dc-ac or dc-dc. The power converter preferably comprises at least one phase leg having two phase arms, at least one of the arm having one or more hybrid device embodiments. However, the power converter may for example be a switched mode power supply (SMPS) of any known topology, e.g., buck, boost, forward, flyback, push-pull, half-or full-bridge, etc. Any one or more main power switches of such an SMPS may comprise a hybrid device as defined herein.
In an implementation, the gate region of the JFET (e.g., well region such as a P well) may be coupled to the first conduction region (source or drain conduction region) of the HEMT by being directly adjacent, i.e., in direct contact with, the first conduction region. However, electrical coupling between the gate region of the JFET and the HEMT first conduction region may be via a contact region, e.g., a source terminal contact of the hybrid device.
Any one or more of the terminals may comprise a semiconductor region and/or a preferably metallic, e.g., gold or aluminium, contact, pad, track and/or wire etc.. Any one or more of the conduction regions of the HEMT and/or JFET preferably comprises a semiconductor material.
The HEMT may have a heterostructure comprising at least one wide bandgap (WBG) semiconductor material. Generally, any WBG material of an embodiment has a bandgap of 3eV or greater. Such a material may further be used in other regions of the HEMT. Such a wide bandgap semiconductor material of the heterostructure may comprise GaN. The heterostructure may comprise e.g., GaN, AIGaN, GaAs, AIGaAs, InGaAn and/or InGaAs. For example, the heterostructure may have example an AIGaN-GaN or GaAs-AIGaAs interface forming a two-dimensional electron gas.
Advantageously, the device may be embodied as a vertical structure, e.g., at least having a vertical structure for the JFET. Such a vertical structure may by more compact than a lateral device wherein generally all regions, including all terminal regions, are fabricated in/on a single surface of the device. In the vertical JFET structure, the drain, drift, gate and source regions may all be fabricated at different vertical layers (the gate region preferably within, and over part of, the drift region).
The heterostructure may comprise a high conductivity channel, preferably in the form of a two-dimensional electron gas (2DEG). Thus, the device (at least the HEMT thereof) may have high channel mobility. Where the heterostructure comprises WBG semiconductor material(s), this may allow operation at higher temperature, higher voltage and/or higher frequencies.
Similarly, the JFET, e.g., an n-channel JFET (preferably having an n-type drift region), may have a drift region comprising a wide bandgap semiconductor material. Such a material may further be used in other regions of the JFET. The wideband semiconductor material of the drift region may comprise SiC. The WBG semiconductor material(s) may as suggested above allow operation at higher temperature, higher voltage and/or higher frequencies.
Thus, a wide band gap semiconductor may be used for either or both of the heterostructure layers and/or for the drift region.
In an embodiment, a first one of the conduction regions (e.g., source) of the JFET may be coupled to a second one of the conduction regions (e.g., drain) of the HEMT (the first HEMT conduction region (e.g. source) generally being coupled to the gate region of the JFET). Such coupling may be by direct contact of the regions, or indeed the first one of the JFET conduction regions may be the same region as the second HEMT conduction region, e.g. both may exist in the form of an N+ GaN region. The coupling may considered as being similar to a cascode circuit arrangement.
There may further be provided the hybrid device, wherein one of said terminals comprises one of the conduction regions of the JFET (the drain terminal preferably comprising the drain region). The other (preferably the source terminal) may be in preferably direct electrical contact (preferably ohmic) with one of the conduction regions (preferably the source) of the HEMT. The gate terminal of the hybrid device may comprise the gate region of the HEMT.
The first conduction region of the JFET may comprise the source conduction region of the JFET.
There may further be provided the hybrid device, wherein a second one of the conduction regions of the HEMT comprises the drain region of the HEMT.
According to another aspect of the present invention, there is provided a combined JFET and HEMT device structure, the structure comprising: a vertical JFET structure comprising: a drain region; a drift region coupled to the drain region; and a well region within the drift region and of opposite conductivity type to the drift region; a HEMT structure fabricated over said JFET structure, the HEMT structure comprising: a heterostructure overlapping said drift region and said well region and having a confined charge carrier region connected between said drift region and said well region.
Similarly to the first aspect, such a device may in embodiments be a normally-off device. The device may for example provide an improvement or alternative to a conventional HEMT, JFET or MOSFET. The vertical FET structure may allow the device to be compact and/or have reduced cost due to a reduced footprint/area on a substrate.
Preferably, the heterostructure layers and/or drift region of the combined JFET and HEMT device structure comprise wide band gap semiconductor. The drift region may for example comprise SiC, preferably doped (e.g., N-).
The combined JFET and HEMT device structure may comprise: a first conducting region connected between said well region and a first part of said confined charge carrier region, the first conducting region proximal to said well region; and a second conducting region connected between said drift region and a second part of said confined charge carrier region, the second conducting region proximal to said drift region. A source region of said JFET may comprise said second conducting region. Such a confined charge carrier region may be a 2DEG. The first conducting region may a doped, e.g., N+, region of, e.g., GaN, between the heterostructure and source terminal. The first conducting region may be located above the well region, e.g., P-well. The first and second parts of the confined charge carrier region may be considered as the laterally opposed ends of the confined charge carrier region. In embodiments, the first conducting region may be directly adjacent the well region and/or the second conducting region directly adjacent to said drift region.
According to another aspect of the present invention, there is provided a method of fabricating a combined JFET and HEMT device structure, comprising: forming a drift region over a substrate having a first conduction terminal; forming a well region in the drift region, the well region having opposite conductivity to the drift region; depositing a first wide bandgap semiconductor layer over the drift region and the well region; depositing a second wide bandgap semiconductor layer over the first wide bandgap semiconductor layer; depositing a second conduction terminal over the well region; and depositing a gate terminal over the second wide bandgap semiconductor layer.
The first conduction terminal may for example comprise a SiC drain region, preferably doped, e.g., N+. The well region may be formed by doping. One of the WBG layers may be, e.g., GaN, and the other, e.g., AIGaN. Either/both is preferably grown by hetero-epitaxy. Any one of the terminals of the combined structure may comprise a contact deposited for example by evaporation. The deposition of the second conduction terminal may comprise prior removal of a region of the first and/or second WBG layers, e.g., by plasma or wet etching.
There may further be provided the method, comprising forming a conduction region over the drift region and separated from the well region by a region of the first wide bandgap semiconductor layer, the conduction region having higher conductivity than the region of the first wide bandgap semiconductor layer. Such a conduction region, e.g., N+ GaN, may be formed for example by doping a region of the first WBG semiconductor layer.
Preferred embodiments are defined in the appended dependent claims.
Any one or more of the above aspects and/or any one or more of the above optional features of the preferred embodiments may be combined, in any permutation. Furthermore, any of the above methods may be provided as a corresponding device, and vice versa.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 shows an example structure of a hybrid GaN-SiC power device; Fig. 2 shows an equivalent circuit of the hybrid GaN-SiC power device; Figs. 3a and 3b show, respectively, the structure and equivalent circuit of a hybrid device embodiment; Figs. 4a and 4b show, respectively, the structure and equivalent circuit of a vertical Si MOSFET; Figs. 5a -5h show an example process for fabricating a hybrid GaN-SiC power device; Fig. 6 shows a flow diagram having steps for forming a hybrid device. The substrate may have been processed to form a conduction region (e.g., drain region) and/or corresponding terminal contact. Such a terminal contact may however be formed/deposited at any other stage, e.g., when a contact of the other conduction terminal (e.g., source region) and/or of the gate terminal is formed/deposited at the 'deposit terminal contact(s)' stage. (Any terminal may comprise a contact and/or semiconductor region); and Fig. 7 shows an example power converter comprising three phase legs each having two phase arms, wherein each power switch of a phase arm may be replaceable by one or more series/parallel hybrid device embodiments.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The following describes embodiments such as a hybrid wide bandgap (WBG) power semiconductor device, preferably a hybrid GaN-SiC power device. The device comprises for example a normally-off GaN HEMT coupled with a SiC JFET, preferably (i.e., optionally) configured similarly to a cascode circuit. Such an embodiment may allow the production of a vertical SiC power switch with normally-off operation and/or a much lower resistance than currently-available SiC MOSFETs. An embodiment preferably has a voltage rating in the 600-900 V range, this range being generally applicable to automotive traction and/or domestic solar inverters, for example.
An embodiment of such a device may out-perform existing Si technology by taking advantage of the merits of both existing GaN and SiC device technologies. Specifically, an embodiment may provide a wide bandgap device which is competitive with existing Si power devices such as Si IGBTs and/or Si superjunction MOSFETs, for example in the above voltage rating range of 600-900 V. Regarding the preferable use of WBG material, it is noted that WBG semiconductors, e.g., having a bandgap of at least 3eV, may allow devices to be formed that operate at higher temperature, higher voltage and/or higher frequency than conventional devices. Generally, wide bandgap power semiconductor device technology has so far largely been focused on two separate areas: gallium nitride (GaN); silicon carbide (SiC).
The structure of an embodiment may be considered as a (e.g., SiC) MOSFET with the MOS channel replaced by a (e.g., GaN) HEMT, preferably to overcome the low mobility (high resistance) of the MOS channel.
Conceptually, an embodiment may be considered as comprising a HEMT combined with a JFET, wherein a JFET conduction region (source or drain) is coupled preferably directly to a conduction region (drain or source) of the HEMT and a control region (gate) of the JFET is coupled preferably directly to the other conduction region of the HEMT.
A basic structure of an embodiment is shown in Fig. 1, with an equivalent conceptual circuit shown in Fig. 2. In Fig. 1, each well and source region (3, 8) may be used for at least one hybrid device, so that the structure of Fig. 1 comprising two wells and sources may be used to implement at least two hybrid devices. In the example, a GaN HEMT is grown on top of a SiC device; the GaN HEMT may effectively control the SiC device, with the latter preferably providing voltage blocking in the off state.
The drawings show elements referable to be the following terms (wherein; represents 'and/or): 1 -Hybrid device; combined JFET and HEMT structure 2 -hybrid device drain terminal; JFET drain (conduction) region; substrate; first conduction terminal (additionally or alternatively, the drain or first conduction terminal may comprise a preferably metallic contact (not shown in Fig. 1) deposited onto the region 2) 3 -hybrid device source terminal; second conduction terminal 4 -hybrid device gate terminal, HEMT gate region
-HEMT
6 -JFET 7 -HEMT source (conduction) region; first conducting region 8 -well region; JFET gate region 9 -JFET source (conduction) region; HEMT drain conduction region; second conducting region -channel; confined charge carrier region 11 -drift region 12a, 12b -heterostructure 13 -first WBG semiconductor layer 14 -second WBG semiconductor layer A comparison with a standard SiC MOSFET can also be made by comparing Figs. 3(a,b) to 4(a,b).
Figs. 5(a) -5(h) show an example process for fabricating the hybrid GaN-SiC power device, the drawings (a) -(h) corresponding respectively to the following: a) start with SiC substrate; b) grow SiC drift region (N-), e.g., epitaxially; c) construct deep p-wells in the SiC drift region; d) grow the first layer of GaN, preferably using hetero-epitaxy, and implant N+ regions to make ohmic contacts for channel; e) complete (preferably epitaxial) GaN/AIGaN top layer growth; f) etch a trench to make the source contact; g) deposit and pattern the source metal; h) deposit and pattern gate electrode.
Advantages of an embodiment may comprise any one or more of the following: * The lattice matching may be good between SiC and GaN, meaning that a high-quality interface between them may be possible.
* The bandgap difference between SiC and GaN may be low, so there may be little heterojunction action to impede the electron flow.
* There may be no need for a bulk substrate of GaN to be provided, since for example the SiC drift region may perform that role.
* The GaN HEMT device may remain a lateral structure, and may in embodiments thus adopt similar construction to existing HEMT devices.
* The GaN HEMT may be normally-off (enhancement mode), in embodiments as per commercially available GaN HEMTs.
* The vertical SiC device may effectively become a SiC JFET coupled with the GaN HEMT, e.g., similarly as in a cascode arrangement. Therefore, the same device construction adopted in existing SiC power JFETs may be adopted in embodiments, preferably with the addition of a GaN HEMT grown on top. (Note that a vertical planar MOSFET may effectively be a lateral MOS channel in cascode with a vertical JFET, irrespective of the semiconductor material).
* Devices with breakdown voltages of 600-900 V may be feasible because resistance of an embodiment is not be limited by a high SIC MOS channel resistance.
* Both device parts (JFET, HEMT) may be operable at high temperature if desired.
Any one or more of the above advantages may be provided in an embodiment wherein the SiC and/or GaN is replaced by different material(s).
No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims (20)

  1. CLAIMS: 1. Hybrid device having a drain terminal, a source terminal and a gate terminal, wherein the hybrid device comprises: a HEMT; and a JFET coupled in series with the HEMT, wherein each of the HEMT and the JFET comprises a gate region, a source conduction region and a drain conduction region, and wherein the gate region of the JFET is coupled to a first said conduction region of the HEMT.
  2. 2. Hybrid device of claim 1, wherein the HEMT has a heterostructure comprising a wide bandgap semiconductor material.
  3. 3. Hybrid device of claim 2, wherein a said wide bandgap semiconductor material of the heterostructure comprises GaN.
  4. 4. Hybrid device of any preceding claim, wherein the JFET has a drift region comprising a wide bandgap semiconductor material.
  5. 5. Hybrid device of any preceding claim, wherein the wideband semiconductor material of the drift region comprises SiC.
  6. 6. Hybrid device of any preceding claim, wherein the JFET is an n-channel JFET.
  7. 7. Hybrid device of any preceding claim, wherein a first one of the conduction regions of the JFET is coupled to a second one of the conduction regions of the HEMT.
  8. 8. Hybrid device of any preceding claim, wherein one of said drain and source terminals of the hybrid device comprises one of the conduction regions of the JFET and the other is in contact with one of the conduction regions of the HEMT, and wherein the gate terminal of the hybrid device comprises the gate region of the HEMT.
  9. 9. Hybrid device of any preceding claim, wherein the first conduction region of the JFET comprises the source conduction region of the JFET.
  10. 10. Hybrid device of any preceding claim, wherein a second one of the conduction regions of the HEMT comprises the drain region of the HEMT.
  11. 11. Hybrid device of any preceding claim, wherein the hybrid device comprises a vertical JFET structure.
  12. 12. Hybrid device of any preceding claim, operable within a 600V to 900V range of source-drain voltage.
  13. 13. A power converter comprising a hybrid device of any preceding claims, the power converter preferably having at least one phase arm comprising a power switch, wherein the power switch comprises the hybrid device.
  14. 14. A combined JFET and HEMT device structure, the structure comprising: a vertical JFET structure comprising: a drain region; a drift region coupled to the drain region; and a well region within the drift region and of opposite conductivity type to the drift region; a HEMT structure fabricated over said JFET structure, the HEMT structure comprising: a heterostructure overlapping said drift region and said well region and having a confined charge carrier region connected between said drift region and said well region.
  15. 15. The combined JFET and HEMT device structure of claim 14, wherein at least one of the heterostructure and drift region comprise wide band gap semiconductor.
  16. 16. The combined JFET and HEMT device structure of claim 14 or 15, comprising: a first conducting region connected between said well region and a first part of said confined charge carrier region, the first conducting region proximal to said well region; and a second conducting region connected between said drift region and a second part of said confined charge carrier region, the second conducting region proximal to said drift region.
  17. 17. The combined JFET and HEMT device structure of claim 16, wherein a source region of said JFET comprises said second conducting region.
  18. 18. Method of fabricating a combined JFET and HEMT device structure, comprising: forming a drift region over a substrate having a first conduction terminal; forming a well region in the drift region, the well region having opposite conductivity to the drift region; depositing a first wide bandgap semiconductor layer over the drift region and the well region; depositing a second wide bandgap semiconductor layer over the first wide bandgap semiconductor layer; depositing a second conduction terminal over the well region; and depositing a gate terminal over the second wide bandgap semiconductor layer.
  19. 19. The method of claim 18, comprising forming a conduction region over the drift region and separated from the well region by a region of the first wide bandgap semiconductor layer, the conduction region having higher conductivity than the region of the first wide bandgap semiconductor layer.
  20. 20. Hybrid device as described and/or illustrated herein.
GB1422127.9A 2014-12-12 2014-12-12 Hybrid device Withdrawn GB2534544A (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130088280A1 (en) * 2011-10-07 2013-04-11 Transphorm Inc. High power semiconductor electronic components with increased reliability

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